Features
•
8-bit Microcontroller Compatible with MCS
®
51 Products
•
Enhanced 8051 Architecture
– Single Clock Cycle per Byte Fetch
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 128 x 8 Internal RAM
– 4-level Interrupt Priority
Nonvolatile Program Memory
– 2K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: Minimum 10,000 Write/Erase Cycles
– Data Retention: Minimum 10 Years
– Serial Interface for Program Downloading
– 32-byte Fast Page Programming Mode
– 64-byte User Signature Array
– 2-level Program Memory Lock for Software Security
Peripheral Features
– Two 16-bit Enhanced Timer/Counters
– Two 8-bit PWM Outputs (AT89LP213 only)
– Enhanced UART with Automatic Address Recognition and Framing Error
Detection (AT89LP214 only)
– Enhanced Master/Slave SPI with Double-buffered Send/Receive
– Programmable Watchdog Timer with Software Reset
– Analog Comparator with Selectable Interrupt and Debouncing
– 8 General-purpose Interrupt Pins
Special Microcontroller Features
– Two-wire On-chip Debug Interface
– Brown-out Detection and Power-on Reset with Power-off Flag
– Internal RC Oscillator
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
I/O and Packages
– Up to 12 Programmable I/O Lines
– Configurable I/O with Quasi-bidirectional, Input, Push-pull Output, and
Open-drain Modes
– 5V Tolerant I/O
– 14-lead TSSOP or PDIP
Operating Conditions
– 2.4V to 5.5V V
CC
Voltage Range
– -40° C to 85°C Temperature Range
•
•
8-bit
Microcontroller
with 2K Bytes
Flash
AT89LP213
AT89LP214
Preliminary
•
•
•
1. Description
The AT89LP213/214 is a low-power, high-performance CMOS 8-bit microcontroller
with 2K bytes of In-System Programmable Flash memory. The device is manufactured
using Atmel's high-density nonvolatile memory technology and is compatible with the
industry-standard MCS-51 instruction set. The AT89LP213/214 is built around an
enhanced CPU core that can fetch a single byte from memory every clock cycle.
In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instruc-
tions to execute in 12, 24 or 48 clock cycles. In the AT89LP213/214 CPU, instructions
need only 1 to 4 clock cycles providing 6 to 12 times more throughput than the stan-
dard 8051. Seventy percent of instructions need only as many clock cycles as they
3538A–MICRO–7/06
have bytes to execute, and most of the remaining instructions require only one additional clock.
The enhanced CPU core is capable of 20 MIPS throughput whereas the classic 8051 CPU can
deliver only 4 MIPS at the same current consumption. Conversely, at the same throughput as
the classic 8051, the new CPU core runs at a much lower speed and thereby greatly reduces
power consumption.
The AT89LP213/214 provides the following standard features: 2K bytes of In-System Program-
mable Flash memory, 128 bytes of RAM, up to 12 I/O lines, two 16-bit timer/counters, two PWM
outputs (AT89LP213 only), a programmable watchdog timer, a full duplex serial port
(AT89LP214 only), a serial peripheral interface, an internal RC oscillator, on-chip crystal oscilla-
tor, and a four-level, six-vector interrupt system.
The two timer/counters in the AT89LP213/214 are enhanced with two new modes. Mode 0 can
be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit
auto-reload timer/counter. In addition, the timer/counters on the AT89LP213 may independently
drive a pulse width modulation output.
The I/O ports of the AT89LP213/214 can be independently configured in one of four operating
modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input mode, the
ports are tristated. Push-pull output mode provides full CMOS drivers and open-drain mode pro-
vides just a pull-down. In addition, all 8 pins of Port 1 can be configured to generate an interrupt
using the general-purpose interrupt interface. The I/O pins of the AT89LP213/214 tolerate volt-
ages higher than the device’s own power supply, up to 5.5V. When the device is supplied at
2.4V and all I/O ports receive 5.5V, the total back flowing current an all I/Os is less than 100 µA.
2. Pin Configuration
2.1
AT89LP213: 14-lead TSSOP/PDIP
(GPI5/MOSI) P1.5
(GPI7/SCK) P1.7
(GPI5/RST) P1.3
GND
(GPI2) P1.2
(T0) P3.4
(INT0/XTAL1) P3.2
1
2
3
4
5
6
7
14
13
12
11
10
9
8
P1.6 (MISO/GPI6)
P1.4 (SS/GPI4)
P1.1 (AIN1/GPI1)
P1.0 (AIN0/GPI0)
VCC
P3.5 (T1)
P3.3 (XTAL2/CLKOUT/INT1)
2.2
AT89LP214: 14-lead TSSOP/PDIP
(GPI5/MOSI) P1.5
(GPI7/SCK) P1.7
(GPI5/RST) P1.3
GND
(GPI2) P1.2
(RxD) P3.0
(INT0/XTAL1) P3.2
1
2
3
4
5
6
7
14
13
12
11
10
9
8
P1.6 (MISO/GPI6)
P1.4 (SS/GPI4)
P1.1 (AIN1/GPI1)
P1.0 (AIN0/GPI0)
VCC
P3.1 (TxD)
P3.3 (XTAL2/CLKOUT/INT1)
2
AT89LP213/214 [Preliminary]
3538A–MICRO–7/06
AT89LP213/214 [Preliminary]
3. Pin Description
Table 3-1.
Pin
AT89LP213
Pin Description
Type
I/O
I/O
I
I/O
I/O
I
I/O
I
I
I
I
I/O
I
I/O
I/O
I/O
I
Description
P1.5:
User-configurable I/O Port 1 bit 5.
MOSI:
SPI master-out/slave-in. When configured as master, this pin is an output. When configured as
slave, this pin is an input.
GPI5:
General-purpose Interrupt input 5.
P1.7:
User-configurable I/O Port 1 bit 7.
SCK:
SPI Clock. When configured as master, this pin is an output. When configured as slave, this pin is
an input.
GPI7:
General-purpose Interrupt input 7.
P1.3:
User-configurable I/O Port 1 bit 3 (if Reset Fuse is disabled).
RST:
External
Active-Low
Reset input (if Reset Fuse is enabled.
See “External Reset” on page 15).
GPI3:
General-purpose Interrupt input 3.
DCL:
Serial Clock input for On-chip Debug Interface when OCD is enabled.
Ground
P1.2:
User-configurable I/O Port 1 bit 2.
GPI2:
General-purpose Interrupt input 2.
P3.4:
User-configurable I/O Port 3 bit 4.
T0:
Timer/Counter 0 External Input or PWM Output.
P3.2:
User-configurable I/O Port 3 bit 2.
XTAL1:
Input to the inverting oscillator amplifier and internal clock generation circuits. It may be used as
a port pin if the internal RC oscillator is selected as the clock source.
DDA:
Serial Data input/output for On-chip Debug Interface when OCD is enabled and the internal RC
oscillator is selected as the clock source.
P3.3:
User-configurable I/O Port 3 bit 3.
XTAL2:
Output from inverting oscillator amplifier. It may be used as a port pin if the internal
RC oscillator is selected as the clock source.
CLKOUT:
When the internal RC oscillator is selected as the clock source, may be used to output the
internal clock divided by 2.
DDA:
Serial Data input/output for On-chip Debug Interface when OCD is enabled and the external
clock is selected as the clock source.
P3.5:
User-configurable I/O Port 3 bit 5.
T1:
Timer/Counter 1 External input or PWM output.
Supply Voltage
P1.0:
User-configurable I/O Port 1 bit 0.
AIN0:
Analog Comparator Positive input.
GPI0:
General-purpose Interrupt input 0.
P1.1:
User-configurable I/O Port 1 bit 1.
AIN1:
Analog Comparator Negative input.
GPI1:
General-purpose Interrupt input 1
P1.4:
User-configurable I/O Port 1 bit 4.
SS:
SPI slave select input.
GPI4:
General-purpose Interrupt input 4.
P1.6:
User-configurable I/O Port 1 bit 6.
MISO:
SPI master-in/slave-out. When configured as master, this pin is an input. When configured
as slave, this pin is an output.
GPI6:
General-purpose Interrupt input 6.
Symbol
1
P1.5
2
P1.7
3
P1.3
4
5
6
GND
P1.2
P3.4
7
P3.2
I/O
I/O
O
8
P3.3
O
I/O
I/O
I/O
I
I/O
I
I
I/O
I
I
I/O
I
I
I/O
I/O
I
9
10
11
P3.5
VDD
P1.0
12
P1.1
13
P1.4
14
P1.6
3
3538A–MICRO–7/06
Table 3-2.
Pin
AT89LP214
Pin Description
Type
I/O
I/O
I
I/O
I/O
I
I/O
I
I
I
I
I/O
I
I/O
I
I/O
I
Description
P1.5:
User-configurable I/O Port 1 bit 5.
MOSI:
SPI master-out/slave-in. When configured as master, this pin is an output. When configured as
slave, this pin is an input.
GPI5:
General-purpose Interrupt input 5.
P1.7:
User-configurable I/O Port 1 bit 7.
SCK:
SPI Clock. When configured as master, this pin is an output. When configured as slave, this pin is
an input.
GPI7:
General-purpose Interrupt input 7.
P1.3:
User-configurable I/O Port 1 bit 3 (if Reset Fuse is disabled).
RST:
External
Active-Low
Reset input (if Reset Fuse is enabled.
See “External Reset” on page 15).
GPI3:
General-purpose Interrupt input 3.
DCL:
Serial Clock input for On-chip Debug Interface.
Ground
P1.2:
User-configurable I/O Port 1 bit 2.
GPI2:
General-purpose Interrupt input 2.
P3.0:
User-configurable I/O Port 3 bit 0.
RXD:
Serial Port Receiver input.
P3.2:
User-configurable I/O Port 3 bit 2.
XTAL1:
Input to the inverting oscillator amplifier and internal clock generation circuits. It may be used as
a port pin if the internal RC oscillator is selected as the clock source.
DDA:
Serial Data input/output for On-chip Debug Interface when OCD is enabled and the internal RC
oscillator is selected as the clock source.
P3.3:
User-configurable I/O Port 3 bit 3.
XTAL2:
Output from inverting oscillator amplifier. It may be used as a port pin if the internal
RC oscillator is selected as the clock source.
CLKOUT:
When the internal RC oscillator is selected as the clock source, may be used to output the
internal clock divided by 2.
DDA:
Serial Data input/output for On-chip Debug Interface when OCD is enabled and the external clock
is selected as the clock source.\
P3.1:
User-configurable I/O Port 3 bit 1.
TXD:
Serial Port Transmitter output.
Supply Voltage
P1.0:
User-configurable I/O Port 1 bit 0.
AIN0:
Analog Comparator Positive input.
GPI0:
General-purpose Interrupt input 0.
P1.1:
User-configurable I/O Port 1 bit 1.
AIN1:
Analog Comparator Negative input.
GPI1:
General-purpose Interrupt input 1
P1.4:
User-configurable I/O Port 1 bit 4.
SS:
SPI slave select input.
GPI4:
General-purpose Interrupt input 4.
P1.6:
User-configurable I/O Port 1 bit 6.
MISO:
SPI master-in/slave-out. When configured as master, this pin is an input. When configured
as slave, this pin is an output.
GPI6:
General-purpose Interrupt input 6.
Symbol
1
P1.5
2
P1.7
3
P1.3
4
5
6
GND
P1.2
P3.0
7
P3.2
I/O
I/O
O
8
P3.3
O
I/O
I/O
O
I
I/O
I
I
I/O
I
I
I/O
I
I
I/O
I/O
I
9
10
11
P3.1
VDD
P1.0
12
P1.1
13
P1.4
14
P1.6
4
AT89LP213/214 [Preliminary]
3538A–MICRO–7/06
AT89LP213/214 [Preliminary]
4. Block Diagram
Figure 4-1.
AT89LP213 Block Diagram
Single
Cycle
8051
CPU
SPI
2KB Flash
Timer 0
Timer 1
128 Bytes
RAM
Analog
Comparator
Port
3
Configurable I/O
Watchdog
Timer
Port 1
Configurable I/O
On-Chip
RC Oscillator
General-purpose
Interrupt
CPU Clock
Configurable
Oscillator
Crystal or
Resonator
Figure 4-2.
AT89LP214 Block Diagram
Single Cycle
8051 CPU
UART
2KB Flash
SPI
128 Bytes
RAM
Timer 0
Timer 1
Port 3
Configurable I/O
Analog
Comparator
Port 1
Configurable I/O
Watchdog
Timer
General-purpose
Interrupt
On-Chip
RC Oscillator
CPU Clock
Configurable
Oscillator
Crystal or
Resonator
5
3538A–MICRO–7/06
ADI参考电路
