Features
•
High-performance and Low-power AVR
®
8-bit RISC Architecture
– 118 Powerful Instructions – Most Single Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
Data and Non-volatile Program Memory
– 4K Bytes of In-System Programmable Flash
Endurance 1,000 Write/Erase Cycles
– 128 Bytes of SRAM
– 256 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– Expanded 16-bit Timer/Counter with Separate Prescaler,
Compare, Capture Modes and 8-, 9-, or 10-bit PWM
– On-chip Analog Comparator
– Programmable Watchdog Timer with Separate On-chip Oscillator
– Programmable UART
– 6-channel, 10-bit ADC
– Master/Slave SPI Serial Interface
Special Microcontroller Features
– Brown-out Reset Circuit
– Enhanced Power-on Reset Circuit
– Low-power Idle and Power-down Modes
Power Consumption at 4 MHz, 3V, 25°C
– Active: 3.4 mA
– Idle Mode: 1.4 mA
– Power-down Mode: <1 µA
I/O and Packages
– 20 Programmable I/O Lines
– 28-lead PDIP and 32-lead TQFP
Operating Voltage
– 2.7V - 6.0V for the AT90LS4433
– 4.0V - 6.0V for the AT90S4433
Speed Grades
– 0 - 4 MHz for the AT90LS4433
– 0 - 8 MHz for the AT90S4433
•
•
•
8-bit
Microcontroller
with 4K Bytes of
In-System
Programmable
Flash
AT90S4433
AT90LS4433
Not Recommend for
New Designs. Use
ATmega8.
•
•
•
•
Rev. 1042H–AVR–04/03
1
Pin Configurations
TQFP Top View
PD2 (INT0)
PD1 (TXD)
PD0 (RXD)
RESET
PC5 (ADC5)
PC4 (ADC4)
PC3 (ADC3)
PC2 (ADC2)
32
31
30
29
28
27
26
25
(INT1) PD3
(T0) PD4
NC
VCC
GND
NC
XTAL1
XTAL2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
PC1 (ADC1)
PC0 (ADC0)
NC
AGND
AREF
NC
AVCC
PB5 (SCK)
RESET
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(T0) PD4
VCC
GND
XTAL1
XTAL2
(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP) PB0
(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP) PB0
(OC1) PB1
(SS) PB2
(MOSI) PB3
(MISO) PB4
PDIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PC5 (ADC5)
PC4 (ADC4)
PC3 (ADC3)
PC2 (ADC2)
PC1 (ADC1)
PC0 (ADC0)
AGND
AREF
AVCC
PB5 (SCK)
PB4 (MISO)
PB3 (MOSI)
PB2 (SS)
PB1 (OC1)
2
AT90S/LS4433
1042H–AVR–04/03
AT90S/LS4433
Description
The AT90S4433 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the AT90S4433
achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to
optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction, executed in one
clock cycle. The resulting architecture is more code efficient while achieving throughputs
up to ten times faster than conventional CISC microcontrollers.
The AT90S4433 provides the following features: 4K bytes of In-System Programmable
Flash, 256 bytes of EEPROM, 128 bytes of SRAM, 20 general purpose I/O lines, 32
general purpose working registers, two flexible Timer/Counters with compare modes,
internal and external interrupts, a programmable serial UART, 6-channel, 10-bit ADC,
programmable Watchdog Timer with internal Oscillator, an SPI serial port and two soft-
ware-selectable Power-saving modes. The Idle mode stops the CPU while allowing the
SRAM, Timer/Counters, SPI port and interrupt system to continue functioning. The
Power-down mode saves the register contents but freezes the Oscillator, disabling all
other chip functions until the next interrupt or Hardware Reset.
The device is manufactured using Atmel’s high-density non-volatile memory technology.
The On-chip Flash Program memory can be re-programmed In-System through an SPI
serial interface or by a conventional non-volatile memory programmer. By combining a
RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel
AT90S4433 is a powerful microcontroller that provides a highly flexible and cost-effec-
tive solution to many embedded control applications.
The AT90S4433 AVR is supported with a full suite of program and system development
tools including: C Compilers, macro assemblers, program debugger/simulators, In-Cir-
cuit Emulators and evaluation kits.
Table 1.
Comparison Table
Device
AT90S4433
AT90LS4433
Flash
4K
4K
EEPROM
256B
256B
SRAM
128B
128B
Voltage Range
4.0V - 6.0V
2.7V - 6.0V
Frequency
0 - 8 MHz
0 - 4 MHz
3
1042H–AVR–04/03
Block Diagram
Figure 1.
The AT90S4433 Block Diagram
PC0 - PC5
VCC
PORTC DRIVERS
GND
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
8-BIT DATA BUS
AVCC
ANALOG MUX
AGND
AREF
ADC
XTAL1
INTERNAL
OSCILLATOR
OSCILLATOR
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
XTAL2
RESET
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
X
Y
Z
TIMER/
COUNTERS
INSTRUCTION
DECODER
INTERRUPT
UNIT
CONTROL
LINES
ALU
EEPROM
STATUS
REGISTER
PROGRAMMING
LOGIC
SPI
UART
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
+
-
ANALOG
COMPARATOR
PORTB DRIVERS
PORTD DRIVERS
PB0 - PB5
PD0 - PD7
4
AT90S/LS4433
1042H–AVR–04/03
AT90S/LS4433
Pin Descriptions
VCC
GND
Port B (PB5..PB0)
Supply voltage.
Ground.
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors. The Port B output
buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port B also serves the functions of various special features of the AT90S4433 as listed
on page 73.
The Port B pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
Port C (PC5..PC0)
Port C is a 6-bit bi-directional I/O port with internal pull-up resistors. The Port C output
buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. Port C also serves as the analog inputs to
the A/D Converter.
The Port C pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output
buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port D also serves the functions of various special features of the AT90S4433 as listed
on page 81.
The Port D pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
RESET
Reset input. An External Reset is generated by a low level on the RESET pin. Reset
pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter
pulses are not guaranteed to generate a reset.
Input to the inverting oscillator amplifier and input to the internal clock operating circuit
Output from the inverting oscillator amplifier
AVCC is the supply voltage for Port A and the A/D Converter. If the ADC is not used,
this pin must be connected to V
CC
. If the ADC is used, this pin should be connected to
V
CC
via a low-pass filter. See page 64 for details on operation of the ADC.
AREF is the analog reference input for the A/D Converter. For ADC operations, a volt-
age in the range 2.0V to AVCC must be applied to this pin.
If the board has a separate analog ground plane, this pin should be connected to this
ground plane. Otherwise, connect to GND.
XTAL1
XTAL2
AVCC
AREF
AGND
5
1042H–AVR–04/03
FPGA/CPLD
