Features
•
Low-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
– 2.7 (V
CC
= 2.7V to 5.5V)
– 1.8 (V
CC
= 1.8V to 5.5V)
User-selectable Internal Organization
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
3-wire Serial Interface
Sequential Read Operation
2 MHz Clock Rate (5V)
Self-timed Write Cycle (10 ms Max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Automotive Grade, Extended Temperature, and Lead-free/Halogen-free
Devices Available
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP, 8-lead TSSOP,
and 8-ball dBGA2
™
Packages
3-wire Serial
EEPROMs
2K (256 x 8 or 128 x 16)
4K (512 x 8 or 256 x 16)
Description
The AT93C56A/66A provides 2048/4096 bits of serial electrically erasable program-
mable read-only memory (EEPROM) organized as 128/256 words of 16 bits each
when the ORG pin is connected to VCC and 256/512 words of 8 bits each when it is
tied to ground. The device is optimized for use in many industrial and commercial
applications where low-power and low-voltage operations are essential. The
AT93C56A/66A is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead
EIAJ SOIC, 8-lead MAP, 8-lead TSSOP, and 8-ball dBGA2™ packages.
AT93C56A
AT93C66A
Advance
Information
Pin Configurations
Pin Name
CS
SK
DI
DO
GND
VCC
ORG
DC
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Internal Organization
Don’t Connect
8-lead MAP
8-lead PDIP
8-lead TSSOP
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
DC
ORG
GND
8-ball dBGA2
VCC
DC
ORG
GND
8
7
6
5
1
2
3
4
8-lead SOIC
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
DC
ORG
GND
CS
SK
DI
DO
Bottom View
VCC
DC
ORG
GND
8
7
6
5
1
2
3
4
CS
SK
DI
DO
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
DC
ORG
GND
Rev. 3378F–SEEPR–04/04
Bottom View
1
The AT93C56A/66A is enabled through the Chip Select pin (CS) and accessed via a
3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a READ instruction at DI, the address is decoded and the data is
clocked out serially on the data output pin DO. The WRITE cycle is completely self-
timed and no separate ERASE cycle is required before WRITE. The WRITE cycle is
only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is brought
“high” following the initiation of a WRITE cycle, the DO pin outputs the READY/BUSY
status of the part.
The AT93C56A/66A is available in 2.7V to 5.5V and 1.8V to 5.5V versions.
Absolute Maximum Ratings*
Operating Temperature......................................−55°C to +125°C
Storage Temperature
.........................................−65°C
to +150°C
Voltage on Any Pin
with Respect to Ground
........................................ −1.0V
to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Block Diagram
Note:
When the ORG pin is connected to VCC, the x 16 organization is selected. When it is
connected to ground, the x 8 organization is selected. If the ORG pin is left unconnected
and the application does not load the input beyond the capability of the internal 1 Meg
ohm pullup, then the x 16 organization is selected. The feature is not available on the
1.8V devices.
2
3378F–SEEPR–04/04
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0V (unless otherwise noted).
Symbol
C
OUT
C
IN
Note:
Test Conditions
Output Capacitance (DO)
Input Capacitance (CS, SK, DI)
1. This parameter is characterized and is not 100% tested.
Max
5
5
Units
pF
pF
Conditions
V
OUT
= 0V
V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from: T
AI
=
−
40°C to +85°C, V
CC
= +1.8V to +5.5V,
T
AE
=
−
40°C to +125°C, V
CC
= +1.8V to +5.5V (unless otherwise noted).
Symbol
V
CC1
V
CC2
V
CC3
I
CC
I
SB1
I
SB2
I
SB3
I
IL
I
OL
V
IL1(1)
V
IH1(1)
V
IL2(1)
V
IH2(1)
V
OL1
V
OH1
V
OL2
V
OH2
Note:
Parameter
Supply Voltage
Supply Voltage
Supply Voltage
READ at 1.0 MHz
Supply Current
Standby Current
Standby Current
Standby Current
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
V
CC
= 5.0V
V
CC
= 1.8V
V
CC
= 2.7V
V
CC
= 5.0V
V
IN
= 0V to V
CC
V
IN
= 0V to V
CC
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
2.7V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
2.7V
I
OL
= 2.1 mA
I
OH
=
−0.4
mA
I
OL
= 0.15 mA
I
OH
=
−100
µA
V
CC
−
0.2
2.4
0.2
−0.6
2.0
−0.6
V
CC
x 0.7
WRITE at 1.0 MHz
CS = 0V
CS = 0V
CS = 0V
Test Condition
Min
1.8
2.7
4.5
0.5
0.5
0
6.0
17
0.1
0.1
Typ
Max
5.5
5.5
5.5
2.0
2.0
0.1
10.0
30
3.0
3.0
0.8
V
CC
+ 1
V
CC
x 0.3
V
CC
+ 1
0.4
Unit
V
V
V
mA
mA
µA
µA
µA
µA
µA
V
V
V
V
V
V
1. V
IL
min and V
IH
max are reference only and are not tested.
3
3378F–SEEPR–04/04
AC Characteristics
Applicable over recommended operating range from T
AI
=
−
40°C to + 85°C, T
AE
=
−
40°C to +125°C, V
CC
= As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
f
SK
Parameter
SK Clock
Frequency
SK High Time
SK Low Time
Minimum CS
Low Time
CS Setup Time
DI Setup Time
CS Hold Time
DI Hold Time
Output Delay to “1”
Output Delay to “0”
CS to Status Valid
CS to DO in High
Impedance
Write Cycle Time
5.0V, 25°C, Page Mode
Test Condition
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
Relative to SK
Relative to SK
Relative to SK
Relative to SK
AC Test
AC Test
AC Test
AC Test
CS = V
IL
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
Min
0
0
0
250
1000
250
1000
250
1000
50
200
100
400
0
100
400
250
1000
250
1000
250
1000
150
400
10
t
WP
Endurance
(1)
4.5V
≤
V
CC
≤
5.5V
0.1
1M
3
Typ
Max
2
1
0.25
Units
MHz
t
SKH
t
SKL
t
CS
t
CSS
t
DIS
t
CSH
t
DIH
t
PD1
t
PD0
t
SV
t
DF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
4
3378F–SEEPR–04/04
Instruction Set for the AT93C56A and AT93C66A
Instruction
READ
EWEN
ERASE
WRITE
ERAL
SB
1
1
1
1
1
Op
Code
10
00
11
01
00
Address
x8
A
8
– A
0
11XXXXXXX
A
8
– A
0
A
8
– A
0
10XXXXXXX
x 16
A
7
– A
0
11XXXXXX
A
7
– A
0
A
7
– A
0
10XXXXXX
D
7
– D
0
D
15
– D
0
x8
Data
x 16
Comments
Reads data stored in memory, at
specified address.
Write enable must precede all
programming modes.
Erases memory location A
n
– A
0
.
Writes memory location A
n
– A
0
.
Erases all memory locations. Valid
only at V
CC
= 4.5V to 5.5V.
D
7
– D
0
D
15
– D
0
Writes all memory locations. Valid
only at V
CC
= 5.0V ±10% and Disable
Register cleared.
Disables all programming instructions.
WRAL
EWDS
Note:
1
1
00
00
01XXXXXXX
00XXXXXXX
01XXXXXX
00XXXXXX
The X’s in the address field represent don’t care values and must be clocked.
Functional Description
The AT93C56A/66A is accessed via a simple and versatile 3-wire serial communication
interface. Device operation is controlled by seven instructions issued by the host pro-
cessor.
A valid instruction starts with a rising edge of CS
and consists of a Start Bit
(logic “1”) followed by the appropriate Op Code and the desired memory address
location.
READ (READ):
The Read (READ) instruction contains the address code for the mem-
ory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C56A/66A
supports sequential read operations. The device will automatically increment the inter-
nal address pointer and clock out the next memory location as long as Chip Select (CS)
is held high. In this case, the dummy bit (logic “0”) will not be clocked out between mem-
ory locations, thus allowing for a continuous stream of data to be read.
ERASE/WRITE (EWEN):
To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the EWEN state, programming remains enabled
until an EWDS instruction is executed or V
CC
power is removed from the part.
ERASE (ERASE):
The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
ERASE instruction and address are decoded. The DO pin outputs the READY/BUSY
status of the part if CS is brought high after being kept low for a minimum of 250 ns (t
CS
).
A logic “1” at pin DO indicates that the selected memory location has been erased, and
the part is ready for another instruction.
5
3378F–SEEPR–04/04
