ATA6826C
Triple Half-bridge DMOS Output Driver with Serial Input
Control
DATASHEET
Features
●
Supply voltage up to 40V
●
R
DSon
typically 0.8 at 25°C, Maximum 1.5 at 150°C
●
Up to 1.0A output current
●
Three half-bridge outputs formed by three high-side and three low-side drivers
●
Capable of switching all kinds of loads such as DC motors, bulbs, resistors,
capacitors and inductors
●
No shoot-through current
●
Very low quiescent current I
S
< 2µA in Standby Mode versus total temperature
range
●
Outputs short-circuit protected
●
Overtemperature protection for each switch and overtemperature prewarning
●
Undervoltage protection
●
Various diagnostic functions such as shorted output, open-load, overtemperature
and power-supply fail detection
●
Serial data interface, daisy chain capable, up to 2MHz clock frequency
●
SO14 power package
9213E-AUTO-06/14
1.
Description
The Atmel
®
ATA6826C is a fully protected triple half-bridge designed in smart power SOI Technology, used to control up to
three different loads by a microcontroller in automotive and industrial applications.
Each of the three high-side and three low-side drivers is capable of driving currents up to 1.0A. The drivers are internally
connected to form three half-bridges and can be controlled separately from a standard serial data interface. Therefore, all
kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC design especially supports the
application of H-bridges to drive DC motors.
Protection is guaranteed regarding short-circuit conditions, overtemperature and undervoltage. Various diagnostic functions
and a very low quiescent current in standby mode opens a wide range of applications. Automotive qualification gives added
value and enhanced quality for exacting requirements of automotive applications.
Figure 1-1. Block Diagram
n.
u.
n.
u.
O
C
S
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
3
VS
Input register
Output register
DI
5
P
S
F
O
P
L
S
C
D
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
H
S
3
Serial interface
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
Charge
pump
CLK
6
CS
4
Fault
detect
Fault
detect
Fault
detect
UV
protection
11
INH
10
Control
logic
VCC
DO
9
Power-on
reset
1
7
GND
GND
GND
GND
Fault
detect
Fault
detect
Fault
detect
Thermal
protection
13
OUT1
8
14
2
OUT3
12
OUT2
2
ATA6826C [DATASHEET]
9213E–AUTO–06/14
2.
Pin Configuration
Figure 2-1. Pinning SO14
GND
OUT3
VS
CS
DI
CLK
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
GND
OUT1
OUT2
VCC
INH
DO
GND
Table 2-1.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Description
Symbol
GND
OUT3
VS
CS
DI
CLK
GND
GND
DO
INH
VCC
OUT2
OUT1
GND
Function
Ground; reference potential; internal connection to pin 7, 8 and 14; cooling tab
Half-bridge output 3; formed by internally connected power MOS high-side switch 3 and low-
side switch 3 with internal reverse diodes; short-circuit protection; overtemperature protection;
diagnosis for short and open load
Power supply for output stages OUT1, OUT2 and OUT3, internal supply
Chip select input; 5V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled
Serial data input; 5V CMOS logic level input with internal pull down; receives serial data from
the control device; DI expects a 16-bit control word with LSB being transferred first
Serial clock input; 5V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (f
max
= 2MHz)
Ground; see pin 1
Ground; see pin 1
Serial data output; 5V CMOS logic level tristate output for output (status) register data; sends
16-bit status information to the microcontroller (LSB is transferred first); output will remain
tri-stated unless device is selected by CS = low, therefore, several ICs can operate on only
one data output line.
Inhibit input; 5V logic input with internal pull down; low = standby, high = normal operation
Logic supply voltage (5V)
Half-bridge output 2; see pin 2
Half-bridge output 1; see pin 2
Ground; see pin 1
ATA6826C [DATASHEET]
9213E–AUTO–06/14
3
3.
3.1
Functional Description
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and is accepted on
the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the
rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of
CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears.
LSB (bit 0, TP) is transferred first.
Figure 3-1. Data Transfer
CS
DI
SRR
LS1
HS1
LS2
HS2
LS3
HS3
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
OCS
13
n. u.
n. u.
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
CLK
DO
TP
S1L
S1H
S2L
S2H
S3L
S3H
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
SCD
OPL
PSF
Table 3-1.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Input Data Protocol
Input Register
SRR
LS1
HS1
LS2
HS2
LS3
HS3
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
OCS
n. u.
n. u.
Function
Status register reset (high = reset; the bits PSF, OPL and SCD in the output data
register are set to low)
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
See LS1
See HS1
See LS1
See HS1
Not used
Not used
Not used
Not used
Not used
Not used
Overcurrent shutdown (high = overcurrent shutdown is active)
Not used
Not used
4
ATA6826C [DATASHEET]
9213E–AUTO–06/14
Table 3-2.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Output Data Protocol
Output (Status)
Register
TP
Status LS1
Status HS1
Status LS2
Status HS2
Status LS3
Status HS3
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
SCD
OPL
PSF
Function
Temperature prewarning: high = warning
High = output is on, low = output is off; not affected by SRR
High = output is on, low = output is off; not affected by SRR
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Not used
Not used
Not used
Not used
Not used
Not used
Short circuit detected: set high when at least one high-side or low-side switch is
switched off by a short-circuit condition. Bits 1 to 6 can be used to detect the
shorted switch.
Open load detected: set high, when at least one active high-side or low-side switch
sinks/sources a current below the open load threshold current.
Power-supply fail: undervoltage at pin VS detected
After power-on reset, the input register has the following status:
Bit 15 Bit 14
x
x
Bit 13
(OCS)
H
Bit 12 Bit 11
x
x
Bit 10
x
Bit 9
x
Bit 8
x
Bit 7
x
Bit 6
(HS3)
L
Bit 5
(LS3)
L
Bit 4
(HS2)
L
Bit 3 Bit 2 Bit 1
(LS2) (HS1) (LS1)
L
L
L
Bit 0
(SRR)
L
The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during normal
operation.
Bit 15 Bit 14
H
H
H
H
H
H
Bit 13
(OCS)
H
H
H
Bit 12 Bit 11 Bit 10
H
L
L
H
L
L
L
H
L
Bit 9
L
H
L
Bit 8
L
L
H
Bit 7
L
L
H
Bit 6
(HS3)
L
L
L
Bit 5
(LS3)
L
L
L
Bit 4
(HS2)
L
L
L
Bit 3 Bit 2 Bit 1
(LS2) (HS1) (LS1)
L
L
L
L
L
L
L
L
L
Bit 0
(SRR)
L
L
L
ATA6826C [DATASHEET]
9213E–AUTO–06/14
5
