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Comprehensive Library of Standard Logic and I/O Cells
Up to 6.5 usable Mgates equivalent NAND2
Operating voltage 1.8V for core and 3.3V or 2.5V for I/O’s
Memory Cells Compiled or synthesized to the Requirements of the Design
EDAC Library
Cold Sparing Buffers
High Speed LVDS Buffers (655Mbps)
PCI Buffers
MQFP Package Up to 352 Pins (336 Signal Pins)
MLGA Packages Up to 625 Pins (575 Signal Pins)
ESD better than 2000V for I/O and better than 1000V for PLL
Predefined Die Sizes to Accommodate Standardized Packages
Space Multi Project Wafer - SMPW - possibility
No single event latch-up below a LET threshold of 95 Mev/mg/cm² at 125°
C
SEU hardened flip-flops
Tested up to a total dose of 300 krads (Si) according to Mil Std 883 Test Method 1019
Quality Grades: QML-Q and QML-V with 5962-06B02, ESCC 9000
Rad. Hard
0.18 µm CMOS
Cell-based ASIC
for Space Use
ATC18RHA
Description
The ATC18RHA asic family provides high-performance and high-density solutions for
space applications. ATC18RHA is fabricated on a 0.18 µm, five-metal-layers CMOS
process intended for use with a supply voltage of 1.8V for core. It offers up to 6.5 mil-
lion routable gates and more than 800 pads.
The ATC18RHA family is supported by a combination of state-of-art third-party and
proprietary design tools: Synopsys, Mentor and Cadence are the reference front end
and back end tools suppliers.
The ATC18RHA asic family is available in several quality assurance grades, such as
Mil-Prf 38535 QML-Q and QML-V and ESCC 9000.
4261G–AERO–02/11
Overview
Introduction
The ASIC “ATC18RHA Design Manual” presents all the required information and flows for
0.18µm designs for aerospace applications, allowing users to view Atmel specific or standard
commercial tool kits and methodological details for actual implementations.
This offering is a 0.18µm CMOS technology based, specified with the 3.3V or 2.5V range for the
periphery (it should be noticed that mixed supply is not allowed), and with the 1.8V range for the
core. The technology parameters and some extra features are described here after.
Periphery
Buffers Description
The peripheral buffer, so called pad, is the electrical interface between the external signals (volt-
age range from 2.3 to 3.6V) and the internal core signals (from 1.65 to 1.95V).
All I/O pads are
Cold Sparing
and
tolerant,
they contains:
• Bidirectional pads
• Tristate Output pads
• Output Only pads
• Input Only pads
(Inverting,Non-Inverting,Schmitt Trigger)
Furthermore the Bidirectional, Tristate Ouputs and Input Only pads are available with or without
Pull-Up or Pull-Down structures.
Specific pads have been developed in 3.3V and 2.5V:
•
LVDS
transmitter and Receiver differential pads
Cold sparing and tolerant only when they are disabled (ien=’1’ or oen=’1’)
•
LVPECL
Receiver differential pads
And, in 3.3V only:
• Cold sparing
PCI
Bidirectional, Tristate Output and Output Only pads
Clusters
The periphery of the chip (pad ring) can be split into several I/O segments
(I/O clusters), some
clusters can be unpowered while others are active.
A specific Power control line is distributed inside the cluster to be able to force all the I/Os of the
cluster in tristate mode whatever their initial state is (ie: an output only buffer will also be turned
to HiZ mode).
Double Pad Ring
In order to increase the number of programmable I/O’s, Atmel proposes the double pad ring con-
figuration. The number of pads on the inner ring will be tailored to the actual need of each
design.
Core supplies are automatically routed to the inner ring. As long as the inner ring of the double
pad ring configuration is used only for core supply pads, the designs are produceable to space
quality levels. During feasibility study, an investigation will be conducted to evaluate if additional
pads, and how many, can be added in the inner ring to be used as I/O’s and still be produced in
space quality level. Anyhow, the resulting total number of pads in the inner ring will not go above
maximum number given in table 2.
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ATC18RHA
4261G–AERO–02/11
ATC18RHA
Core
Standard cell library
The Atmel Standard Cell Library contains a comprehensive set of a combination of logic and
storage cells, including cells that belong to the following categories:
• Buffers and Gates
• PLL
• Multiplexers
• Standard and SEU Hardened Flip-flops
• Standard and SEU Hardened Scan Flip-flops
• Latches
• Adders and Subtractors
Memory Hard Blocks
The ATC18RHA memory libraries are developed from Virage memory compilers. All these mem-
ories are synchronous.
It can compile single-port synchronous SRAM, dual port (2RW) synchronous SRAM and Two-
port (1W,1R) synchronous Register-File.
For maximum block sizes, see the design manual.
Array Organization
Though ATC18RHA is a standard cell library, pre-defined matrix sizes and pad frames have
been set so as to ease the assembly of every individual ASIC design by sticking to presently
available package cavity sizes and layouts. These are close in size to MH1RT matrix sizes.
The following tables give, for each matrix, for a single or a double pad ring configuration, the
maximum number of pads on the outer ring, the maximum number of pads implementable on the
inner ring, and the resulting typical gate count capability of each matrix.
Table 1.
Single Pad Ring Standard Arrays Dimensions and Integration Capabilities
Name
ATC18RHA95_216
ATC18RHA95_324
ATC18RHA95_404
ATC18RHA95_504
ATC18RHA95_544
MH1RT Equivalence
NA
MH1099E
MH1156E
MH1242E
NA
Size (mm)
6.19x6.19
8.76x8.76
10.66x10.66
13.03x13.03
14.03x14.03
Pads
216
324
404
504
544
Usable Gates (typ)
1M
2.2M
3.5M
5.5M
6.5M
Table 2.
Double Pad Ring Standard Arrays Dimensions and Integration Capabilities
Name
ATC18RHA95_216D
ATC18RHA95_324D
ATC18RHA95_404D
ATC18RHA95_504D
ATC18RHA95_544D
Outer Ring Programmable
Pads
216
324
404
504
544
Inner Ring Max
Number of Pads
88
140
180
232
252
Size (mm)
6.19x6.19
8.76x8.76
10.66x10.66
13.03x13.03
14.03x14.03
Usable Gates (typ)
0.725M
1.8M
2.97M
4.83M
5.71M
3
4261G–AERO–02/11
Design
Management
Introduction
Atmel used to propose different design modes, where each mode indicated the designer respon-
sibilities, the design location and the design tools. With designs becoming more complex, timing
and power constraints more severe, and design behaviour more technology dependent, Atmel
believes that any design must be a close cooperation between the customer and the manufac-
turer. Therefore, only one design scenario is retained: the ASIC chip is designed by the
customer, at his site with a set of design tools supported by Atmel.
The development of an ASIC chip can be split into 4 main phases.
A meeting is set between each phase.
Figure 1.
Design Management Phases
Design Phases
During the review meetings, the conformity of the design to Atmel rules is checked and acknowl-
edged in formal documents, and the data is transferred to the next phase. The content of each
phase and responsibilities are described in the ‘ATC18RHA design manual’.
Deliverables
Table 3.
Deliverables at the end of each phase
DESIGN PHASE
DELIVERABLE
ASIC feasibility study report (APF-tc-FSR-project code).
Design start review document (APF-tc-DSR-project code).
ASIC logic review document (APF-tc-LR-project code) +
Files as required in the document.
LOGIC DESIGN
Updated DSR document
ASIC design review document (APF-tc-DR-project code) +
Files as required in the document.
PHYSICAL DESIGN
PROTOTYPES MANUFACTURING
& TEST
Updated DSR document
Packaged parts and associated documents
WHO
FEASIBILITY STUDY
Atmel
CUSTOMER
Atmel
CUSTOMER
Atmel
Atmel
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ATC18RHA
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ATC18RHA
Design Flows
Introduction
This chapter summarizes the design flow with reference to different platforms used for Cell
based chip design. For further details, refer to the ATC18RHA design manual.
Figure 2.
Global design flow
Atmel Package Assistant is running on SUN stations under SOLARIS and on LINUX PC (Red-
Hat distribution from version 7.0). Design Kits are compatible with both platforms depending on
third party tools availability. Hardware platform memory requirement is design dependant.
Design Kit
The use of both external and internal ICCAD tools requires the modelization of each library ele-
ment. The set of required files for all the supported CAD tools relevant to the ATC18RHA family
is called the
ATC18RHA Design Kit.
These files describe the functionality, including or not tim-
ings and other attributes, with respect to each targeted tools modelization features and methods.
The design kit contains relevant descriptions of standard cells and peripheral cells, given for dif-
ferent pre-defined ranges of temperature, voltage and process.
5
4261G–AERO–02/11
