Features
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Operates between 2.7V to 5.5V
•
High-density, High-performance Electrically-erasable Complex
Programmable Logic Device
– 44-pin, 32 I/O CPLD
– 100% connected
– 12 ns Maximum Pin-to-pin Delay
– Registered Operation up to 90.9 MHz
– Fully Connected Input and Feedback Logic Array
Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
Advanced Power Management Features
– Pin-controlled 5 µA Standby Mode (Typical)
– Programmable Pin-keeper Inputs and I/Os
Available in Commercial and Industrial Temperature Ranges
Available in 44-lead PLCC and TQFP Packages
Advanced EEPROM Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latchup Immunity
Supported by Popular Third-party Tools
Security Fuse Feature
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High-
performance
EE PLD
ATF1500ABV
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Description
The ATF1500ABV is a high-performance, high-density complex PLD. Built on an
advanced EEPROM technology, it has maximum pin-to-pin delays of 12 ns and sup-
ports sequential logic operation at speeds up to 90.9 MHz. With 32 logic macrocells
and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI and classic
PLDs.
Pin Configurations
Pin
Name
CLK
I
I/O
GCLR
OE1,
OE2
VCC
PD
Function
Clock
Logic Inputs
Bi-directional
Buffers
Register Reset
(active low)
Output Enable
(active low)
(+3V to 5.25V)
Supply
Power-down
(active high)
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
PLCC
Top View
I/O
I/O
I/O/PD
VCC
OE2/I
GCLR/I
OE1/I
CLK/I
GND
I/O
I/O
TQFP
Top View
I/O
I/O
I/O/PD
VCC
OE2/I
GCLR/I
OE1/I
CLK/I
GND
I/O
I/O
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
GND
I/O
I/O
44
43
42
41
40
39
38
37
36
35
34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
Rev. 0723I–08/01
1
Functional Logic Diagram
(1)
Note:
1. Arrows connecting macrocells indicate direction and groupings of CASIN/CASOUT data flow.
2
ATF1500ABV
0723I–08/01
ATF1500ABV
The ATF1500ABV’s 100% connected global input and feedback architecture simplifies logic
placement and eliminates pinout changes due to design changes. Any Macrocell may be con-
nected to any I/O pin.
The ATF1500ABV has 32 bi-directional I/O pins and four dedicated input pins. Each dedicated
input pin can also serve as a global control signal: register clock, register reset or output
enable. Each of these control signals can be selected for use individually within each
macrocell.
Each of the 32 logic macrocells generates a buried feedback, which goes to the global bus.
Each input and I/O pin also feeds into the global bus. Because of this global busing, each of
these signals is always available to all 32 macrocells in the device.
Each macrocell also generates a foldback logic term, which goes to a regional bus. All signals
within a regional bus are connected to all 16 macrocells within the region.
Cascade logic between macrocells in the ATF1500ABV allows fast, efficient generation of
complex logic functions. The ATF1500ABV contains four such logic chains, each capable of
creating sum term logic with a fan-in of up to 40 product terms.
Bus-friendly
Pin-keeper
Input and I/Os
All input and I/O pins on the ATF1500ABV have programmable “data-keeper” circuits. If acti-
vated, when any pin is driven high or low and then subsequently left floating, it will stay at that
previous high or low level.
This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels
that cause unnecessary power consumption and system noise. The keeper circuits eliminate
the need for external pull-up resistors and eliminate their DC power consumption.
Pin-keeper circuits can be disabled. Programming is controlled in the logic design file. Once
the pin-keeper circuits are disabled, normal termination procedures are required for unused
inputs and I/Os.
Speed/Power
Management
The ATF1500ABV has several built-in speed and power management features. The
ATF1500ABV contains circuitry that automatically puts the device into a low-power standby
mode when no logic transitions are occurring. This not only reduces power consumption dur-
ing inactive periods, but also provides proportional power savings for most applications
running at system speeds below 10 MHz.
All ATF1500ABVs also have an optional pin-controlled power-down mode. In this mode, cur-
rent drops to typically 2 mA. When the power-down option is selected, the PD pin is used to
power-down the part. The power-down option is selected in the design source file. When
enabled, the device goes into power-down when the PD pin is high. In the power-down mode,
all internal logic signals are latched and held, as are any enabled outputs. All pin transitions
are ignored until the PD is brought low. When the power-down feature is enabled, the PD can-
not be used as a logic input or output. However, the PD pin’s macrocell may still be used to
generate buried foldback and cascade logic signals.
Each output also has individual slew rate control. This may be used to reduce system noise by
slowing down outputs that do not need to operate at maximum speed. Outputs default to slow
switching, and may be specified as fast switching in the design file.
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0723I–08/01
Input Diagram
V
CC
INPUT
100K
ESD
PROTECTION
CIRCUIT
PROGRAMMABLE
OPTION
I/O Diagram
V
CC
OE
DATA
I/O
V
CC
100K
PROGRAMMABLE
OPTION
Design
Software
Support
ATF1500ABV designs are supported by several third-party tools. Automated fitters allow logic
synthesis using a variety of high level description languages and formats.
4
ATF1500ABV
0723I–08/01
ATF1500ABV
ATF1500ABV Macrocell
ATF1500ABV
Macrocell
The ATF1500ABV macrocell is flexible enough to support highly complex logic functions oper-
ating at high speed. The macrocell consists of five sections: product terms and product term
select multiplexer; OR/XOR/CASCADE logic; a flip-flop; output select and enable; and logic
array inputs.
Each ATF1500ABV macrocell has five product terms. Each product term receives as its inputs
all signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as needed to
the macrocell logic gates and control signals. The PTMUX programming is determined by the
design compiler, which selects the optimum macrocell configuration.
Product Terms
and Select Mux
OR/XOR/
CASCADE Logic
The ATF1500ABV macrocell’s OR/XOR/CASCADE logic structure is designed to efficiently
support all types of logic. Within a single macrocell, all the product terms can be routed to the
OR gate, creating a five-input AND/OR sum term. With the addition of the CASIN from neigh-
boring macrocells, this can be expanded to as many as 40 product terms with little small
additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic func-
tions. One input to the XOR comes from the OR sum term. The other XOR input can be a
product term or a fixed high or low level. For combinatorial outputs, the fixed-level input allows
output polarity selection. For registered functions, the fixed levels allow De Morgan minimiza-
tion of the product terms. The XOR gate is also used to emulate JK-type flip-flops.
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0723I–08/01
