SAMA5D2 Series
Atmel | SMART ARM-based Embedded MPU
DATASHEET
Introduction
The Atmel
®
| SMART SAMA5D2 series is a high-performance, ultra-low-power
ARM
®
Cortex
®
-A5 processor-based MPU running up to 500 MHz, with support for
multiple memories such as DDR2, DDR3, DDR3L, LPDDR1, LPDDR2, LPDDR3,
and QSPI Flash. The devices integrate powerful peripherals for connectivity and
user interface applications, and offer advanced security functions (ARM
TrustZone
®
, tamper detection, secure data storage, etc.), as well as high-
performance crypto-processors AES, SHA and TRNG.
The SAMA5D2 series is delivered with a free Atmel Linux distribution and bare
metal C examples.
Features
ARM Cortex-A5 core
̶
ARMv7-A architecture
̶
ARM TrustZone
̶
NEON
™
Media Processing Engine
̶
Up to 500 MHz
̶
ETM/ETB 8 Kbytes
Memory Architecture
̶
Memory Management Unit
̶
32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache
̶
128-Kbyte L2 cache configurable to be used as an internal SRAM
̶
One 128-Kbyte scrambled internal SRAM
̶
One 160-Kbyte internal ROM
64-Kbyte scrambled and maskable ROM embedding Atmel boot loader/Atmel
Secure boot loader
96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table
̶
̶
High-bandwidth scramblable 16-bit or 32-bit Double Data Rate (DDR)
multiport dynamic RAM controller supporting up to 512 Mbyte 8-bank
DDR2/DDR3 (DLL off only)/DDR3L (DLL off
only)/LPDDR1/LPDDR2/LPDDR3, including “on-the-fly”
encryption/decryption path
8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code
(PMECC)
Atmel-11267E-ATARM-SAMA5D2-Datasheet_25-Jul-16
System running up to 166 MHz in typical conditions
̶
Reset controller, shutdown controller, periodic interval timer, independent watchdog timer and secure Real-Time
Clock (RTC) with clock calibration
̶
One 600 to 1200 MHz PLL for the system and one 480 MHz PLL optimized for USB high speed
̶
Digital fractional PLL for audio (11.2896 MHz and 12.288 MHz)
̶
Internal low-power 12 MHz RC and 32 KHz typical RC
̶
Selectable 32.768-Hz low-power oscillator and 8 to 24 MHz oscillator
̶
51 DMA Channels including two 16-channel 64-bit Central DMA Controllers
̶
64-bit Advanced Interrupt Controller (AIC)
̶
64-bit Secure Advanced Interrupt Controller (SAIC)
̶
Three programmable external clock signals
Low-Power Modes
̶
Ultra Low-power mode with fast wakeup capability
̶
Low-power Backup mode with 5-Kbyte SRAM and SleepWalking
™
features
Wakeup from up to nine wakeup pins, UART reception, analog comparison
Fast wakeup capability
Extended Backup mode with DDR in Self-Refresh mode
Peripherals
̶
LCD TFT controller up to 1024x768, with four overlays, rotation, post-processing and alpha blending, 24-bit
parallel RGB
̶
ITU-R BT. 601/656/1120 Image Sensor Controller (ISC) supporting up to 5 M-pixel sensors with a parallel 12-bit
interface for Raw Bayer, YCbCr, Monochrome and JPEG-compressed sensor interface
̶
Two Synchronous Serial Controllers (SSC), two Inter-IC Sound Controllers (
I
2
S
C), and one Stereo Class D
amplifier
̶
One Pulse Density Modulation Interface Controller (PDMIC)
̶
One USB high-speed device port (UDPHS) and one USB high-speed host port or two USB high-speed host
ports (UHPHS)
̶
One USB high-speed host port with a High-Speed Inter-Chip (HSIC) interface
̶
One 10/100 Ethernet MAC (GMAC)
Energy efficiency support (IEEE 802.3az standard)
Ethernet AVB support with IEEE802.1AS time stamping
IEEE802.1Qav credit-based traffic-shaping hardware support
IEEE1588 Precision Time Protocol (PTP)
̶
Two high-speed memory card hosts:
SDMMC0: SD 3.0, eMMC 4.51, 8 bits
SDMMC1: SD 2.0, eMMC 4.41, 4 bits only
̶
̶
̶
̶
̶
̶
̶
̶
̶
̶
̶
Two master/slave Serial Peripheral Interfaces (SPI)
Two Quad Serial Peripheral Interfaces (QSPI)
Five FLEXCOMs (USART, SPI and TWI)
Five UARTs
Two master CAN-FD (MCAN) controllers with SRAM-based mailboxes, and time- and event-triggered
transmission
One Rx only UART in backup area (RXLP)
One analog comparator (ACC) in backup area
Two 2-wire interfaces (TWIHS) up to 400 Kbits/s supporting the I
2
C protocol and SMBUS (TWIHS)
Two 3-channel 32-bit Timer/Counters (TC), supporting basic PWM modes
One full-featured 4-channel 16-bit Pulse Width Modulation (PWM) controller
One 12-channel, 12-bit, Analog-to-Digital Converter (ADC) with Resistive TouchScreen capability
2
SAMA5D2 Series [DATASHEET]
Atmel-11267E-ATARM-SAMA5D2-Datasheet_25-Jul-16
Safety
̶
Zero-power Power-On Reset (POR) cells
̶
Main crystal clock failure detector
̶
Write-protected registers
̶
Integrity Check Monitor (ICM) based on SHA256
̶
Memory Management Unit
̶
Independent watchdog
Security
̶
5 Kbytes of internal scrambled SRAM:
1 Kbyte non-erasable on tamper detection
4 Kbytes erasable on tamper detection
̶
̶
̶
Note:
256 bits of scrambled and erasable registers
Eight tamper pins for static or dynamic intrusion detections
Environmental monitors on secured versions: temperature, voltage, frequency and active die shield
For
environmental monitors, r
efer to datasheet “SAMA5D2 Security Module” (Atmel literature No. 44036), available
under Non-Disclosure Agreement (NDA). Contact an Atmel Sales Representative for details.
̶
Note:
Atmel Secure Boot
For secure boot strategies, refer to application note “SAMA5D2x Secure Boot Strategy” (Atmel literature No. 44040),
available under Non-Disclosure Agreement (NDA). Contact an Atmel Sales Representative for details.
̶
̶
̶
On-the-fly AES encryption/decryption on DDR and QSPI memories (AESB)
RTC including time-stamping on security intrusions
Programmable fuse box with 544 fuse bits (including JTAG protection and BMS)
Hardware cryptography
̶
SHA (SHA1, SHA224, SHA256, SHA384, SHA512): compliant with FIPS PUB 180-2
̶
AES: 256-, 192-, 128-bit key algorithm, compliant with FIPS PUB 197
̶
TDES: two-key or three-key algorithms, compliant with FIPS PUB 46-3
̶
True Random Number Generator (TRNG) compliant with NIST Special Publication 800-22 Test Suite and FIPS
PUBs 140-2 and 140-3
Up to 128 I/Os
̶
Fully programmable through set/clear registers
̶
Multiplexing of up to eight peripheral functions per I/O line
̶
Each I/O line can be assigned to a peripheral or used as a general purpose I/O
̶
The PIO controller features a synchronous output providing up to 32 bits of data output in one write operation
Packages
̶
289-ball LFBGA, 14 x 14 mm body, 0.8 mm pitch
̶
256-ball TFBGA, 8 x 8 mm body, 0.4 mm pitch
̶
196-ball TFBGA, 11 x 11 mm body, 0.75 mm pitch
SAMA5D2 Series [DATASHEET]
Atmel-11267E-ATARM-SAMA5D2-Datasheet_25-Jul-16
3
1.
Description
The Atmel | SMART SAMA5D2 Series is a high-performance, power-efficient embedded MPU based on the ARM
Cortex-A5 processor. It integrates the ARM NEON SIMD engine for accelerated multimedia and signal processing,
a configurable 128-Kbyte L2 cache, a floating point unit for high-precision computing and reliable performance, as
well as high data bandwidth architecture. The device features an advanced user interface and connectivity
peripherals. Advanced security is provided by powerful cryptographic accelerators, by the ARM TrustZone
technology securing access to memories and sensitive peripherals, and by several hardware features that
safeguard memory content, authenticate software reliability, detect physical attacks and prevent information
leakage during code execution.
The SAMA5D2 features an internal multilayer bus architecture associated with 2 x 16 DMA channels and
dedicated DMAs for the communication and interface peripherals required to ensure uninterrupted data transfers
with minimal processor overhead. The device supports DDR2, DDR3, DDR3L, LPDDR1, LPDDR2, LPDDR3, and
SLC/MLC NAND Flash memory up to 32-bit ECC.
The comprehensive peripheral set includes an LCD TFT controller with overlays for hardware-accelerated image
composition, an image sensor controller, audio support through I
2
S, SSC, a stereo Class D amplifier and a digital
microphone. Connectivity peripherals include a 10/100 EMAC, USBs, CAN-FDs, FLEXCOMs, UARTs, SPIs and
two QSPIs, SDIO/SD/e.MMCs, and TWIs/I
2
C.
Protection of code and data is provided by automatic scrambling of memories and an Integrity Check Monitor
(ICM) to detect any modification of the memory contents. The SAMA5D2 also supports execution of encrypted
code (QSPI or one portion of the DDR) with an “on-the-fly” encryption-decryption process.
With its secure design architecture, cryptographic acceleration engines, and secure boot loader, the SAMA5D2 is
the ideal solution for point-of-sale (POS), IoT and industrial applications requiring anti-cloning, data protection and
secure communication transfer.
SAMA5D2 devices feature three software-selectable low-power modes: Idle, Ultra-low-power and Backup.
In Idle mode, the processor is stopped while all other functions can be kept running.
In Ultra-low-power-mode 0, the processor is stopped while all other functions are clocked at 512 Hz and interrupts
or peripherals can be configured to wake up the system based on events, including partial asynchronous wakeup
(SleepWalking).
In Ultra-low-power mode 1, all clocks and functions are stopped but some peripherals can be configured to wake
up the system based on events, including partial asynchronous wakeup (SleepWalking).
In Backup mode, RTC and wakeup logic are active. The Backup mode can be extended to feature DDR in Self-
refresh mode.
SAMA5D2 devices also include an Event System that allows peripherals to receive, react to and send events in
Active and Idle modes without processor intervention.
4
SAMA5D2 Series [DATASHEET]
Atmel-11267E-ATARM-SAMA5D2-Datasheet_25-Jul-16
2.
Configuration Summary
SAMA5D2 Configuration Summary
SAMA5D21
SAMA5D22
TFBGA196
72
16-bit
128 Kbytes
2
24-bit RGB
1
1
–
1
3
(2 Hosts/
1 HSIC,
or
1 Host/
1 Device/
1 HSIC)
–
2
(2 Hosts
or
1 Host/
1 Device)
2
SAMA5D23
SAMA5D24
TFBGA256
105
16/32-bit
SAMA5D26
SAMA5D27
LFBGA289
128
SAMA5D28
Table 2-1.
Feature
Package
PIOs
DDR Bus
SRAM
QSPI
LCD
Camera Interface
(ISC)
EMAC
CAN
USB
2
(2 Hosts
or
1 Host/1 Device)
3
(2 Hosts/1 HSIC
or
1 Host/1 Device/1 HSIC)
UART/SPI/I
2
C
SDIO/SD/MMC
I
2
S/SSC/
Class D/PDM
ADC Inputs
Timers
PWM
Tamper Pins
AESB
Environmental
Monitors,
Die Shield
–
–
9/6/6
1
2/2/1/1
5
6
4 (PWM) + 5 (TC)
6
Yes
Yes
2
–
–
10 / 7 / 7
2
12
4 (PWM) + 6 (TC)
8
Yes
Yes
For information on device pin compatibility, refer to
Section 5.2 “Pinouts”.
SAMA5D2 Series [DATASHEET]
Atmel-11267E-ATARM-SAMA5D2-Datasheet_25-Jul-16
5
