SAM V71
Atmel | SMART ARM-based Flash MCU
DATASHEET
Introduction
Atmel
®
| SMART SAM V71 is a high-performance Flash microcontroller (MCU)
based on the 32-bit ARM
®
Cortex
®
-M7 RISC (5.04 CoreMark/MHz) processor
with floating point unit (FPU). Designed for Automotive applications, the SAM V71
has been developed and manufactured according to the most stringent
requirements of the international standard ISO-TS-16949. The device operates at
a maximum speed of 300 MHz, features up to 2048 Kbytes of Flash, dual 16-
Kbyte cache memory, up to 384 Kbytes of SRAM and is available in 64-, 100- and
144-pin packages.
The Atmel | SMART SAM V71 offers an extensive peripheral set, including
Ethernet 10/100, dual CAN-FD, High-speed USB Host and Device plus PHY, up
to 8 UARTs, I2S, SD/MMC interface, a CMOS camera interface, system control
and a 12-bit ADC, as well as high-performance crypto-processors AES, SHA and
TRNG.
Features
Core
̶
ARM Cortex-M7 running at up to 300 MHz
(1)
̶
16 Kbytes of ICache and 16 Kbytes of DCache with Error Code Correction
(ECC)
̶
Single- and double-precision HW Floating Point Unit (FPU)
̶
Memory Protection Unit (MPU) with 16 zones
̶
DSP Instructions, Thumb
®
-2 Instruction Set
̶
Embedded Trace Module (ETM) with instruction trace stream, including Trace
Port Interface Unit (TPIU)
Memories
̶
Up to 2048 Kbytes embedded Flash with unique identifier and user signature
for user-defined data
̶
Up to 384 Kbytes embedded Multi-port SRAM
̶
Tightly Coupled Memory (TCM) interface with four configurations
(disabled, 2 x 32 Kbytes, 2 x 64 Kbytes, 2 x 128 Kbytes)
̶
16 Kbytes ROM with embedded Bootloader routines (UART0, USB) and IAP
routines
̶
16-bit Static Memory Controller (SMC) with support for SRAM, PSRAM, LCD
module, NOR and NAND Flash with on-the-fly scrambling
Atmel-44003E-ATARM-SAM V71-Datasheet_12-Oct-16
̶
16-bit SDRAM Controller (SDRAMC) interfacing up to 256 MB and with on-the-fly scrambling
System
̶
Embedded voltage regulator for single-supply operation
̶
Power-on-Reset (POR), Brown-out Detector (BOD) and Dual Watchdog for safe operation
̶
Quartz or ceramic resonator oscillators: 3 to 20 MHz main oscillator with failure detection, 12 MHz or 16 MHz
needed for USB operations. Optional low-power 32.768 kHz for RTC or device clock
̶
RTC with Gregorian calendar mode, waveform generation in low-power modes
̶
RTC counter calibration circuitry compensates for 32.768 kHz crystal frequency variations
̶
32-bit low-power Real-time Timer (RTT)
̶
High-precision Main RC oscillator with 12 MHz default frequency for device startup. In-application trimming
access for frequency adjustment. 8/12 MHz are factory-trimmed.
̶
32.768 kHz crystal oscillator or Slow RC oscillator as source of low-power mode device clock (SLCK)
̶
One 500 MHz PLL for system clock, one 480 MHz PLL for USB high-speed operations
̶
Temperature Sensor
̶
One dual-port 24-channel central DMA Controller (XDMAC)
Low-Power Features
̶
Low-power Sleep, Wait and Backup modes, with typical power consumption down to 1.1 µA in Backup mode
with RTC, RTT and wakeup logic enabled
̶
Ultra-low-power RTC and RTT
̶
1 Kbyte of backup RAM (BRAM) with dedicated regulator
Peripherals
̶
One Ethernet MAC (GMAC) 10/100 Mbps in MII mode and RMII with dedicated DMA. IEEE1588 PTP frames
and 802.3az Energy-efficiency support. Ethernet AVB support with IEEE802.1AS Timestamping and
IEEE802.1Qav credit-based traffic-shaping hardware support.
̶
USB 2.0 Device/Mini Host High-speed (USBHS) at 480 Mbps, 4-Kbyte FIFO, up to 10 bidirectional endpoints,
dedicated DMA
̶
12-bit ITU-R BT. 601/656 Image Sensor Interface (ISI)
̶
Two master Controller Area Networks (MCAN) with Flexible Data Rate (CAN-FD) with SRAM-based mailboxes,
time- and event-triggered transmission
̶
MediaLB
®
device with 3-wire mode, up to 1024 x Fs speed, supporting MOST25 and MOST50 networks
̶
Three USARTs. USART0/1/2 support LIN mode, ISO7816, IrDA
®
, RS-485, SPI, Manchester and Modem
modes; USART1 supports LON mode.
̶
Five 2-wire UARTs with SleepWalking
™
support
̶
Three Two-Wire Interfaces (TWIHS) (I
2
C-compatible) with SleepWalking support
̶
Quad I/O Serial Peripheral Interface (QSPI) interfacing up to 256 MB Flash and with eXecute-In-Place and on-
the-fly scrambling
̶
Two Serial Peripheral Interfaces (SPI)
̶
One Serial Synchronous Controller (SSC) with I2S and TDM support
̶
Two Inter-IC Sound Controllers (I2SC)
̶
One High-speed Multimedia Card Interface (HSMCI) (SDIO/SD Card/e.MMC)
̶
Four Three-Channel 16-bit Timer/Counters (TC) with Capture, Waveform, Compare and PWM modes, constant
on time. Quadrature decoder logic and 2-bit Gray Up/Down Counter for stepper motor
̶
Two 4-channel 16-bit PWMs with complementary outputs, Dead Time Generator and eight fault inputs per PWM
for motor control, two external triggers to manage power factor correction (PFC), DC-DC and lighting control.
̶
Two Analog Front-End Controllers (AFEC), each supporting up to 12 channels with differential input mode and
programmable gain stage, allowing dual sample-and-hold at up to 1.7 Msps. Offset and gain error correction
feature.
̶
One 2-channel 12-bit 1 Msps-per-channel Digital-to-Analog Controller (DAC) with Differential and Over
Sampling modes
2
SAM V71 [DATASHEET]
Atmel-44003E-ATARM-SAM V71-Datasheet_12-Oct-16
̶
One Analog Comparator Controller (ACC) with flexible input selection, selectable input hysteresis
Cryptography
̶
True Random Number Generator (TRNG)
̶
AES: 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB-197 Specifications
̶
Integrity Check Monitor (ICM). Supports Secure Hash Algorithm SHA1, SHA224 and SHA256.
I/O
̶
Up to 114 I/O lines with external interrupt capability (edge- or level-sensitivity), debouncing, glitch filtering and
On-die Series Resistor Termination
̶
Five Parallel Input/Output Controllers (PIO)
Voltage
̶
Single supply voltage from 3.0V to 3.6V
Automotive
̶
Qualification AEC-Q100 grade 2 ([-40°C : +105°C] ambient temperature)
Packages
̶
LQFP144, 144-lead LQFP, 20 x 20 mm, pitch 0.5 mm
̶
TFBGA144, 144-ball TFBGA, 10 x 10 mm, pitch 0.8 mm
̶
LQFP100, 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm
̶
TFBGA100, 100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm
̶
LQFP64, 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm
1.
300 MHz is at [-40°C : +105°C], 1.2V or with the internal regulator.
Notes:
SAM V71 [DATASHEET]
Atmel-44003E-ATARM-SAM V71-Datasheet_12-Oct-16
3
1.
Description
The Atmel | SMART SAM V71 devices are members of a family of Automotive Flash microcontrollers based on the
high-performance 32-bit ARM Cortex-M7 processor with Floating Point Unit (FPU). These devices operate at up to
300 MHz and feature up to 2048 Kbytes of Flash and up to 384 Kbytes of SRAM.
The on-chip SRAM can be configured as Tightly Coupled Memory (TCM) or system memory. A multi-port access
to the SRAM guarantees a minimum access latency.
The peripheral set includes:
Connectivity interfaces
̶
̶
̶
Ethernet MAC (GMAC) with specific hardware support for Audio Video Bridging (AVB)
High-speed USB Device port and a high-speed USB Host port sharing an embedded transceiver
MediaLB (MLB) device interface
̶
̶
̶
High-speed Multimedia Card Interface (HSMCI) for SDIO/SD/e.MMC
External Bus Interface (EBI) featuring an SDRAM Controller
Static Memory Controller providing connection to SRAM, PSRAM, NOR Flash, LCD module and
NAND Flash
̶
̶
̶
̶
̶
̶
̶
̶
̶
Controller Area Networks with Flexible Data Rate (CAN-FD)
Universal Synchronous Asynchronous Receiver Transmitters (USART)
Universal Asynchronous Receiver Transmitters (UART)
Two-wire Interfaces (TWI) supporting the I
2
C protocol
Quad I/O Serial Peripheral Interface (QSPI)
Serial Peripheral Interfaces (SPI)
Serial Synchronous Controller (SSC) supporting I2S and TDM protocols
Inter-IC Sound Controllers (I2SC)
Image Sensor Interface (ISI)
Enhanced Pulse Width Modulators (PWM)
̶
̶
̶
General-purpose 16-bit timers with stepper motor and quadrature decoder logic support
Ultra low-power Real-Time Timer (RTT)
Ultra low-power Real-Time Clock (RTC)
̶
̶
̶
Dual Analog Front-End (AFE) including a 12-bit Analog-to-Digital Converter (ADC), a Programmable
Gain Amplifier (PGA), dual Sample-and-Hold and a digital averaging with up to 16-bit resolution
Dual-channel 12-bit Digital-to-Analog Converter (DAC)
Analog Comparator
̶
̶
̶
High-performance crypto-processors Advanced Encryption Standard (AES)
Secure Hash Algorithm (SHA)
True Random Number Generator (TRNG)
̶
̶
̶
Sleep mode
SleepWalking™ mode
Backup mode
Memory interfaces
Communication interfaces
Control and timing
̶
Integrated analog capability
Cryptography
Power optimization
4
SAM V71 [DATASHEET]
Atmel-44003E-ATARM-SAM V71-Datasheet_12-Oct-16
̶
̶
Clock system optimization
Sending/reacting to events in Active and Sleep modes
The SAM V71 devices have three software-selectable low-power modes: Sleep, Wait and Backup. In Sleep mode,
the processor is stopped while all other functions can be kept running. In Wait mode, all clocks and functions are
stopped but some peripherals can be configured to wake up the system based on predefined conditions. This
feature, called SleepWalking, performs a partial asynchronous wakeup, thus allowing the processor to wake up
only when needed. In Backup mode, RTT, RTC and wakeup logic are running. In addition, in this mode, the device
is able to meet the most stringent Key-Off requirements while retaining 1Kbyte of SRAM.
To optimize power consumption, the clock system has been designed to support different clock frequencies for
selected peripherals. Moreover, the processor and bus clock frequency can be modified without affecting
processing on, for example, the USB, U(S)ART, AFE and Timer Counter.
The SAM V71 devices are also capable of sending and reacting to events in Active and Sleep modes without
processor intervention.
SAM V71 [DATASHEET]
Atmel-44003E-ATARM-SAM V71-Datasheet_12-Oct-16
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