Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Features
s
Description
The CMOS ATT3000 Series Field-Programmable
Gate Array (FPGA) family provides a group of high-
density, digital integrated circuits. Their regular,
extendable, flexible, user-programmable array
architecture is composed of a configuration program
store plus three types of configurable elements: a
perimeter of I/O blocks, a core array of logic blocks,
and resources for interconnection. The general struc-
ture of an FPGA is shown in Figure 1.
The
ORCA
Foundry for ATT3000 Development Sys-
tem provides automatic place and route of netlists.
Logic and timing simulation are available as design
verification alternatives. The design editor is used for
interactive design optimization and to compile the
data pattern that represents the configuration pro-
gram.
The FPGA’s user-logic functions and interconnec-
tions are determined by the configuration program
data stored in internal static memory cells. The pro-
gram can be loaded in any of several modes to
accommodate various system requirements. The
program data resides externally in an EEPROM,
EPROM, or ROM on the application circuit board, or
on a floppy disk or hard disk. On-chip initialization
logic provides for optional automatic loading of pro-
gram data at powerup. A serial configuration PROM
can provide a very simple serial configuration pro-
gram storage.
*
Xilinx, XC3000,
and
XC3100
are registered trademarks of
Xilinx, Inc.
High performance:
— Up to 270 MHz toggle rates
— 4-input LUT delays <2.7 ns
User-programmable gate arrays
— Unlimited reprogrammability
— Easy design iteration through in-system
logic changes
Flexible array architecture:
— Compatible arrays ranging from 1500 to
6000 gate logic complexity
— Extensive register, combinatorial, and I/O
capabilities
— Low-skew clock nets
— High fan-out signal distribution
— Internal 3-state bus capabilities
— TTL or CMOS input thresholds
— On-chip oscillator amplifier
Standard product availability:
— Low-power 0.55 µm CMOS, static memory
technology
— Pin-for-pin compatible with
Xilinx* XC3000*
and
XC3100*
families
— Cost-effective for volume production
— 100% factory pretested
— Selectable configuration modes
ORCA™
Foundry for ATT3000 Development
System support
All FPGAs processed on a QML-certified line
Extensive packaging options
s
s
s
s
s
s
Table 1. ATT3000 Series FPGAs
FPGA
ATT3020
ATT3030
ATT3042
ATT3064
ATT3090
Max
Logic
Gates
1,500
2,000
3,000
4,500
6,000
Typical Gate
Range
1,000—1,500
1,500—2,000
2,000—3,000
3,500—4,500
5,000—6,000
Configurable
Logic
Blocks
64
100
144
224
320
Array
8x8
10 x 10
12 x 12
16 x 14
20 x 16
User I/Os
Max
64
80
96
120
144
Flip-
Flops
256
360
480
688
928
Horizontal
Long Lines
16
20
24
32
40
Configuration
Data Bits
14,779
22,176
30,784
46,064
64,160
ATT3000 Series Field-Programmable Gate Arrays
Data Sheet
February 1997
Table of Contents
Contents
Page
Contents
Page
Features ..................................................................... 1
Description ................................................................. 1
Architecture ................................................................ 3
Configuration Memory................................................ 4
I/O Block ..................................................................... 5
Summary of I/O Options ......................................... 6
Configurable Logic Block ............................................ 7
Programmable Interconnect ....................................... 9
General-Purpose Interconnect ............................. 10
Direct Interconnect ............................................... 11
Long Lines ............................................................ 13
Internal Buses ...................................................... 14
Crystal Oscillator .................................................. 16
Configuration ............................................................ 17
Initialization Phase ............................................... 17
Configuration Data ............................................... 19
Configuration Modes ................................................ 22
Master Mode ........................................................ 22
Peripheral Mode ................................................... 24
Slave Mode .......................................................... 25
Daisy Chain .......................................................... 26
Special Configuration Functions .............................. 27
Input Thresholds ................................................... 27
Readback ............................................................. 27
Reprogram ........................................................... 28
DONE Pull-Up ...................................................... 28
DONE Timing ....................................................... 28
RESET Timing ...................................................... 28
Crystal Oscillator Division .................................... 28
Performance .............................................................29
Device Performance .............................................29
Logic Block Performance ......................................30
Interconnect Performance .....................................30
Power ........................................................................32
Power Distribution .................................................32
Power Dissipation .................................................33
Pin Information .........................................................34
Pin Assignments .......................................................39
Package Thermal Characteristics .............................50
Package Coplanarity .................................................51
Package Parasitics ...................................................51
Absolute Maximum Ratings ......................................53
Electrical Characteristics ..........................................54
Outline Diagrams ......................................................68
Terms and Definitions ...........................................68
44-Pin PLCC .........................................................68
68-Pin PLCC .........................................................69
84-Pin PLCC .........................................................70
100-Pin QFP .........................................................71
100-Pin TQFP .......................................................72
132-Pin PPGA ......................................................73
144-Pin TQFP .......................................................74
160-Pin QFP .........................................................75
175-Pin PPGA ......................................................76
208-Pin SQFP .......................................................77
Ordering Information .................................................78
2
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Architecture
The perimeter of configurable I/O blocks (IOBs) pro-
vides a programmable interface between the internal
logic array and the device package pins. The array of
configurable logic blocks (CLBs) performs user-
specified logic functions. The interconnect resources
are programmed to form networks, carrying logic
signals among blocks, analogous to printed-circuit
board traces connecting MSI/SSI packages.
The blocks’ logic functions are implemented by
programmed look-up tables. Functional options are
implemented by program-controlled multiplexers.
Interconnecting networks between blocks are
implemented with metal segments joined by program-
controlled pass transistors. These functions of the
FPGA are established by a configuration program
which is loaded into an internal, distributed array of
configuration memory cells. The configuration program
is loaded into the FPGA at powerup and may be
reloaded on command. The FPGA includes logic and
control signals to implement automatic or passive
configuration. Program data may be either bit serial or
byte parallel. The
ORCA
Foundry for ATT3000 Devel-
opment System generates the configuration program
bit stream used to configure the FPGA. The memory
loading process is independent of the user logic func-
tions.
Figure 1. Field-Programmable Gate Array Structure
Lucent Technologies Inc.
3
ATT3000 Series Field-Programmable Gate Arrays
Data Sheet
February 1997
Configuration Memory
The static memory cell used for the configuration mem-
ory in the FPGA has been designed specifically for
high reliability and noise immunity. Integrity of the
FPGA configuration memory based on this design is
ensured even under various adverse conditions. Com-
pared with other programming alternatives, static mem-
ory is believed to provide the best combination of high
density, high performance, high reliability, and compre-
hensive testability.
As shown in Figure 2, the basic memory cell consists of
two CMOS inverters plus a pass transistor used for
writing and reading cell data. The cell is only written to
during configuration and only read from during read-
back. During normal operation, the cell provides contin-
uous control and the pass transistor is off and does not
affect cell stability. This is quite different from the opera-
tion of conventional memory devices, in which the cells
are frequently read and rewritten.
The memory cell outputs Q and
Q
use full ground and
V
CC
levels and provide continuous, direct control. The
additional capacitive load and the absence of address
decoding and sense amplifiers provide high stability to
the cell. Due to their structure, the configuration mem-
ory cells are not affected by extreme power supply
excursions or very high levels of alpha particle radia-
tion. Soft errors have not been observed in reliability
testing.
Two methods of loading configuration data use serial
data, while three use byte-wide data. The internal con-
figuration logic utilizes framing information, embedded
in the program data by the
ORCA
Foundry Develop-
ment System, to direct memory cell loading. The serial
data framing and length count preamble provide pro-
gramming compatibility for mixes of various Lucent pro-
grammable gate arrays in a synchronous, serial, daisy-
chain fashion.
READ OR
WRITE
Q CONFIGURATION
CONTROL
Q
DATA
5-3101(F)
Figure 2. Static Configuration Memory Cell
4
Lucent Technologies Inc.
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
I/O Block
Each user-configurable I/O block (IOB), shown in
Figure 3, provides an interface between the external
package pin of the device and the internal user logic.
Each IOB includes both registered and direct input
paths and a programmable 3-state output buffer which
may be driven by a registered or direct output signal.
Configuration options allow each IOB an inversion, a
controlled slew rate, and a high-impedance pull-up.
Each input circuit also provides input clamping diodes
to provide electrostatic protection and circuits to inhibit
latch-up produced by input currents.
The input buffer portion of each IOB provides threshold
detection to translate external signals applied to the
package pin to internal logic levels. The global input-
buffer threshold of the IOB can be programmed to be
compatible with either TTL or CMOS levels. The buff-
ered input signal drives the data input of a storage
element which may be configured as a positive-edge
triggered D flip-flop or a low-level transparent latch. The
sense of the clock can be inverted (negative edge/high
transparent) as long as all IOBs on the same clock net
use the same clock sense. Clock/load signals (IOB pins
.ik and .ok) can be selected from either of two die edge
metal lines. I/O storage elements are reset during con-
figuration or by the active-low chip
RESET
input. Both
direct input (from IOB pin .i) and registered input (from
IOB pin .q) signals are available for interconnect.
PROGRAM-CONTROLLED MEMORY CELLS
V
CC
PASSIVE
PULL UP
OUT
INVERT
3-STATE
INVERT
OUTPUT
SELECT
SLEW
RATE
3-STATE
OUTPUT ENABLE
.t
OUT
.o
D
Q
OUTPUT
BUFFER
FLIP-
FLOP
R
DIRECT IN
REGISTERED IN
.i
.q
Q
D
TTL OR
CMOS
INPUT
THRESHOLD
I/O PAD
FLIP-
FLOP
OR
LATCH
R
.ok
.lk
(GLOBAL RESET)
CK1
CK2
PROGRAM-
CONTROLLED
MULTIPLEXER
= PROGRAMMABLE INTERCONNECTION POINT OR PIP
5-3102(F)
Figure 3. Input/Output Block
Lucent Technologies Inc.
5
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