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ATTINY25-20SNR

IC MCU 8BIT 2KB FLASH 8SOIC

器件类别:嵌入式处理器和控制器    微控制器和处理器   

厂商名称:Microchip(微芯科技)

厂商官网:https://www.microchip.com

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器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
Microchip(微芯科技)
包装说明
SOP, SOP8,.3
Reach Compliance Code
compliant
Factory Lead Time
7 weeks
具有ADC
YES
其他特性
ALSO OPERATES AT 2.7 V MINIMUM SUPPLY AT 10 MHZ
地址总线宽度
位大小
8
CPU系列
AVR RISC
最大时钟频率
20 MHz
DAC 通道
NO
DMA 通道
NO
外部数据总线宽度
JESD-30 代码
R-PDSO-G8
JESD-609代码
e3
长度
5.29 mm
湿度敏感等级
3
I/O 线路数量
6
端子数量
8
最高工作温度
105 °C
最低工作温度
-40 °C
PWM 通道
YES
封装主体材料
PLASTIC/EPOXY
封装代码
SOP
封装等效代码
SOP8,.3
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
峰值回流温度(摄氏度)
260
电源
3/5 V
认证状态
Not Qualified
RAM(字节)
128
ROM(单词)
2048
ROM可编程性
FLASH
座面最大高度
2.16 mm
速度
20 MHz
最大压摆率
8 mA
最大供电电压
5.5 V
最小供电电压
4.5 V
标称供电电压
5 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Matte Tin (Sn)
端子形式
GULL WING
端子节距
1.27 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
40
宽度
5.24 mm
uPs/uCs/外围集成电路类型
MICROCONTROLLER, RISC
文档预览
Atmel 8-bit AVR Microcontroller with 2/4/8K
Bytes In-System Programmable Flash
ATtiny25/V / ATtiny45/V / ATtiny85/V
Summary
Features
High Performance, Low Power AVR
®
8-Bit Microcontroller
Advanced RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
Non-volatile Program and Data Memories
– 2/4/8K Bytes of In-System Programmable Program Memory Flash
• Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes Internal SRAM
– Programming Lock for Self-Programming Flash Program and EEPROM Data Security
Peripheral Features
– 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 8-bit High Speed Timer/Counter with Separate Prescaler
• 2 High Frequency PWM Outputs with Separate Output Compare Registers
• Programmable Dead Time Generator
– USI – Universal Serial Interface with Start Condition Detector
– 10-bit ADC
• 4 Single Ended Channels
• 2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
• Temperature Measurement
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
I/O and Packages
– Six Programmable I/O Lines
– 8-pin PDIP, 8-pin SOIC, 20-pad QFN/MLF, and 8-pin TSSOP (only ATtiny45/V)
Operating Voltage
– 1.8 - 5.5V for ATtiny25V/45V/85V
– 2.7 - 5.5V for ATtiny25/45/85
Speed Grade
– ATtiny25V/45V/85V: 0 – 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny25/45/85: 0 – 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
Industrial Temperature Range
Low Power Consumption
– Active Mode:
• 1 MHz, 1.8V: 300 µA
Rev. 2586QS–AVR–08/2013
– Power-down Mode:
• 0.1 µA at 1.8V
2586QS–AVR–08/2013
1. Pin Configurations
Figure 1-1.
Pinout ATtiny25/45/85
PDIP/SOIC/TSSOP
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
GND
1
2
3
4
8
7
6
5
VCC
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)
NOTE: TSSOP only for ATtiny45/V
QFN/MLF
DNC
DNC
DNC
DNC
DNC
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3
DNC
DNC
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
1
2
3
4
5
20
19
18
17
16
15
14
13
12
11
NOTE: Bottom pad should be soldered to ground.
DNC: Do Not Connect
1.1
1.1.1
Pin Descriptions
VCC
Supply voltage.
GND
Ground.
Port B (PB5:PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
1.1.2
1.1.3
DNC
DNC
GND
DNC
DNC
6
7
8
9
10
VCC
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
DNC
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)
ATtiny25/45/85 [DATASHEET]
2586QS–AVR–08/2013
2
Port B also serves the functions of various special features of the ATtiny25/45/85 as listed in
“Alternate Functions
of Port B” on page 60.
On ATtiny25, the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged in ATtiny15 Compatibility
Mode for supporting the backward compatibility with ATtiny15.
1.1.4
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock
is not running and provided the reset pin has not been disabled. The minimum pulse length is given in
Table 21-4
on page 165.
Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
ATtiny25/45/85 [DATASHEET]
2586QS–AVR–08/2013
3
2. Overview
The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1
MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1.
Block Diagram
8-BIT DATABUS
CALIBRATED
INTERNAL
OSCILLATOR
PROGRAM
COUNTER
VCC
PROGRAM
FLASH
STACK
POINTER
WATCHDOG
TIMER
MCU CONTROL
REGISTER
TIMING AND
CONTROL
SRAM
MCU STATUS
REGISTER
GND
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
DECODER
X
Y
Z
TIMER/
COUNTER0
TIMER/
COUNTER1
UNIVERSAL
SERIAL
INTERFACE
CONTROL
LINES
ALU
STATUS
REGISTER
INTERRUPT
UNIT
PROGRAMMING
LOGIC
DATA
EEPROM
OSCILLATORS
DATA REGISTER
PORT B
DATA DIR.
REG.PORT B
ADC /
ANALOG COMPARATOR
PORT B DRIVERS
RESET
PB[0:5]
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
ATtiny25/45/85 [DATASHEET]
2586QS–AVR–08/2013
4
The ATtiny25/45/85 provides the following features: 2/4/8K bytes of In-System Programmable Flash, 128/256/512
bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one
8-bit Timer/Counter with compare modes, one 8-bit high speed Timer/Counter, Universal Serial Interface, Internal
and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and
three software selectable power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter,
ADC, Analog Comparator, and Interrupt system to continue functioning. Power-down mode saves the register con-
tents, disabling all chip functions until the next Interrupt or Hardware Reset. ADC Noise Reduction mode stops the
CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash
allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional
non-volatile memory programmer or by an On-chip boot code running on the AVR core.
The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools including: C Com-
pilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits.
ATtiny25/45/85 [DATASHEET]
2586QS–AVR–08/2013
5
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