Integrated
Circuit
Systems, Inc.
AV9108
CPU Frequency Generator
General Description
The
AV9108
offers a tiny footprint solution for generating two
simultaneous clocks. One clock, the REFCLK, is a fixed output
frequency which is the same as the input reference crystal (or
clock). The other clock, CLK1, can vary between 2 and 120
MHz, with up to 16 selectable preprogrammed frequencies
stored in internal ROM.
The
ICS9108
is ideal for use in a 3.3V system. It can generate
a 66.66 MHz clock at 3.3V. In addition, the
ICS9108
provides
a symmetrical wave form with a worst case duty cycle of 45/55.
The
ICS9108
has very tight edge control between the CPU
clock and 2XCPU clock outputs, with a worst case skew of
250ps.
The device has advanced features which include on-chip loop
filters, tristate outputs, and power-down capability. A mini-
mum of external components - two decoupling capacitors and
an optional ferrite bead - are all that are required for jitter-free
operation. Standard versions for computer motherboard appli-
cations are the
AV9108-03, AV9108-05
and the
ICS9108-10.
Custom masked versions, with customized frequencies and
features, are available in 6-8 weeks for a small NRE fee.
Features
•
•
•
•
•
•
•
•
•
•
•
Runs up to 80 MHz at 3.3V
50/50 typical duty cycle at 5V
±250ps
absolute jitter
Generates frequencies from 2 to 140 MHz
2 to 32 MHz input reference frequency
Up to 16 frequencies stored internally
Patented on-chip Phase Locked Loop with VCO for clock
generation
Provides reference clock and synthesized clock
On-chip loop filter
Low power 0.8µ CMOS technology
8-pin or 14-pin DIP or SOIC package
Block Diagram
AV 9108 RevB032195
AV9108
Pin Configuration
FS0
GND
X1/ICLK
X2
1
2
3
4
8
7
6
5
REFCLK
VDD
CLK1
FS1
FS1
FS2
FS3
AGND
GND
PD
X1/ICLK
1
2
3
4
5
6
7
14
13
12
11
10
9
8
FS0
REFCLK
VDD
CLK1
OE (CLK1)
OE (REFCLK)
X2
AV9108-05/-10
8-Pin DIP, SOIC
AV9108-03/-11
14-Pin DIP, SOIC
Pin Descriptions for
AV9108-03, AV9108-05 and AV9108-10
PIN NUMBER
-05/-10/-13
1
5
-03
14
1
2
3
4
5
6
7
8
9
10
11
12
13
FS0
FS1
FS2
FS3
AGND
GMD
PD
X1/ICLK
X2
OE(REFCLK)
OE(CLK1)
CLK1
VDD
REFCLK
PIN
NAME
TYPE
Input
Input
Input
Input
-
-
Input
Input
Output
Input
Input
Output
-
Output
DESCRIPTION
Frequency Select 0 for CLK1 (-03 has pull-up).
Frequency Select 1 for CLK1 (-03 has pull-up).
Frequency Select 2 for CLK1 (-03 has pull-up).
Frequency Select 3 for CLK1 (-03 has pull-up).
Analog GROUND.
Digital GROUND.
POWER-DOWN. Shuts off chip when low. Internal pull-up.
CRYSTAL OUTPUT or INPUT CLOCK frequency. Typically 14.318 MHz
system clock.
CRYSTAL OUTPUT (No Connect when clock used.).
OUTPUT ENABLE. Tristates REFCLK when low. Pull-up.
OUTPUT ENABLE. Tristates CLK1 when low. Pull-up.
CLOCK1 Output (see decoding tables).
Digital power supply (+3V DC).
REFERENCE CLOCK output. Produces a buffered version of the input clock or
crystal frequency (typically 14.318 MHz).
2
3
4
6
7
8
2
AV9108
Actual Frequencies
Decoding Table for AV9108-05, 14.318 input
FS1
0
0
1
1
FS0
0
1
0
1
CLK1
40.01 MHz
50.11 MHz
66.61 MHz
80.01 MHz
Decoding Table for AV9108-11 (in MHz)
FS3
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLK1
16.00 MHz
33.39 MHz
50.11 MHz
80.01 MHz
66.58 MHz
100.23 MHz
60.00 MHz
4.01 MHz
8.02 MHz
20.05 MHz
25.06 MHz
39.99 MHz
33.25 MHz
50.11 MHz
30.00 MHz
4.01 MHz
Decoding Table for AV9108-03, 14.318 input
FS3
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLK1
16.00 MHz
39.99 MHz
50.11 MHz
80.01 MHz
66.58 MHz
100.23 MHz
8.02 MHz
4.01 MHz
8.02 MHz
20.00 MHz
25.06 MHz
40.01 MHz
33.29 MHz
50.11 MHz
4.01 MHz
2.05 MHz
Decoding Table for AV9108-10, 14.318 input
FS1
0
0
1
1
FS0
0
1
0
1
CLK1
25.057 MHz
33.289 MHz
40.006 MHz
50.113 MHz
Note: The dash number following ICS9108 must be included when ordering product since it specifies the frequency decoding
table being ordered. Decoding options can be created by a simple metal mask change.
3
AV9108
Frequency Accuracy and Calculation
The accuracy of the frequencies produced by the
ICS9108
depends on the input frequency and the desired actual output
frequency. The formula for calculating the exact frequency is
as follows:
Output Frequency = Input Frequency
×
where A=2, 3, 4 ... 128, and
B=2, 3, 4 ... 32.
For example, to calculate the actual output frequency for a
video monitor expecting a 44.900 MHz clock and using a
14.318 MHz input clock, the closest A/B ratio is 69/22, which
gives an output of 44.906 MHz (within 0.02% of the target
frequency). Generally, the
ICS9108
can produce frequencies
within 0.1% of the desired output.
A
B
Allowable Input and Output Frequencies
The input frequency should be between 2 and 32 MHz and the
A/B ratio should not exceed 24. The output should fall in the
range of 2-120 MHz.
Output Enable
The Output Enable feature tristates the specified output clock
pins. This places the selected output pins in a high impedance
state to allow for system level diagnostic testing.
Power-Down
If equipped, the power-down shuts off the specified PLL or
entire chip to save current. A few milliseconds are required to
reach full functioning speed from a power-down state.
Frequency Transitions
A key
ICS9108
feature is the ability to provide glitch-free frequency transitions across its output frequency range. The
ICS9108
provides smooth transitions between any of the two groups of eight frequencies (when FS3=0 or FS3=1), so that the device will
switch glitch-free between 4-100 MHz and 2-50 MHz.
4
AV9108
Absolute Maximum Ratings
AVDD, VDD referenced to GND . . . . . . . . . . . . . . . 7V
Operating temperature under bias. . . . . . . . . . . . . . . . 0°C to +70°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Electrical Characteristics at 5V
(Operating V
DD
= +4.5V to +5.5V; T
A
=0°C to 70°C unless otherwise stated)
DC Characteristics
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage, Note 1
Output Low Current, Note 1
Output High Current, Note 1
Supply Current
Supply Current
Supply Current
Pull-up Resistor, Note 1
Rise Time 0.8 to 2.0V, Note 1
Fall Time 2.0 to 0.8V, Note 1
Rise Time 20% to 80%, Note 1
Fall Time 80% to 20%, Note 1
Duty Cycle, Note 1
Jitter, One Sigma, Note 1
Jitter, One Sigma, Note 1
Jitter, One Sigma, Note 1
Jitter, Absolute, Note 1
Jitter, Absolute, Note 1
Jitter, Absolute, Note 1
Input Frequency, Note 1
Output Frequency
Power-up Time, Note 1
Transition Time, Note 1
SYMBOL
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
OL
I
OH
I
CC
I
CC
(PD low)
I
CC
(PD low)
R
pu
T
r
T
f
T
r
T
f
D
t
T
jis
T
jis
T
jis
T
jab
T
jab
T
jab
F
i
F
o
T
pu
T
ft
TEST CONDITIONS
MIN
-
2.0
-
-2.0
-
2.4
22.0
-
-
-
-
-
AC Characteristics
15pf load
15pf load
15pf load
15pf load
15pf load @ 1.4V
From 20 to 100 MHz
From 14 to 16 MHz
From 14 to Below
From 20 to 100 MHz
From 14 to 16 MHz
From 14 to Below
-
-
-
-
45.0
-
0.60
0.40
2.0
1.0
50.0
50.0
100.0
0.2
1.40
1.00
3.5
2.5
55.0
150.0
200.0
1.0
250.0
500.0
3.0
19.0
120.0
18.0
13.0
ns
ns
ns
ns
%
ps
ps
%
ps
ps
%
MHz
MHz
ms
ms
TYP
-
-
6.0
-
0.15
3.25
35.0
-50.0
18.0
38.0
14.0
380.0
MAX
0.8
-
16
2.0
0.40
-
-
-35.0
42.0
100.0
40.0
700.0
UNITS
V
V
µA
µA
V
V
mA
mA
mA
µA
µA
k ohms
V
IN
=0V
V
IN
=V
DD
I
OL
=10mA
I
OH
=-30mA
V
OL
=0.8V
V
OH
=2.0V
Unload, 50 MHz
Unload, Logic Inputs 000
Unload, Logic Inputs 111
-250.0
-500.0
11.0
2.0
-
-
1.0
14.3
-
7.58
6.0
8 to 66.6 MHz
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
5
嵌入式系统
