AY0438
32-Segment CMOS LCD Driver
FEATURES
• Drives up to 32 LCD segments of arbitrary config-
uration
• CMOS process for: wide supply voltage range,
low- power operation, high-noise immunity, wide
temperature range
• CMOS and TTL-compatible inputs
• Electrostatic discharge protection on all pins
• Cascadable
• On-chip oscillator
• Requires only three control lines
PIN CONFIGURATION
40-Lead Dual In-line
V
DD
LOAD
SEG 32
SEG 31
SEG 30
SEG 29
SEG 28
SEG 27
SEG 26
SEG 25
SEG 24
SEG 23
SEG 22
SEG 21
SEG 20
SEG 19
SEG 18
SEG 17
SEG 16
SEG 15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CLOCK
SEG 1
SEG 2
SEG 3
V
SS
DATA OUT
DATA IN
SEG 4
SEG 5
LCDΦ
BP
SEG 6
SEG 7
SEG 8
SEG 9
SEG 10
SEG 11
SEG 12
SEG 13
SEG 14
APPLICATIONS
•
•
•
•
Industrial displays
Consumer product displays
Telecom product displays
Automotive dashboard displays
DESCRIPTION
The AY0438 is a CMOS integrated device that drives a
liquid crystal display, usually under microprocessor
control. The part acts as a smart peripheral that drives
up to 32 LCD segments. It needs only three control
lines due to its serial input construction. It latches the
data to be displayed and relieves the microprocessor
from the task of generating the required waveforms.
The AY0438 can drive any standard or custom parallel
drive LCD display, whether it be field effect or dynamic
scattering; 7-, 9-, 14- or 16-segment characters; deci-
mals; leading + or -; or special symbols. Several
AY0438 devices can be cascaded. The AC frequency
of the LCD waveforms can either be supplied by the
user or generated by attaching a capacitor to the LCD
input, which controls the frequency of an internal oscil-
lator.
The AY0438 is available in 40-lead dual in-line plastic
and 44-lead PLCC packages. Unpackaged dice are
also available.
44 PLCC
NC
SEG 30
SEG 31
SEG 32
LOAD
V
DD
CLOCK
SEG 1
SEG 2
SEG 3
V
SS
6
5
4
3
2
1
44
43
42
41
40
AY0438
SEG 29
SEG 28
SEG 27
SEG 26
SEG 25
SEG 24
SEG 23
SEG 22
SEG 21
SEG 20
SEG 19
7
8
9
10
11
12
13
14
15
16
17
AY0438
39
38
37
36
35
34
33
32
31
30
29
NC
DATA OUT
DATA IN
SEG 4
SEG 5
LCDΦ
BP
SEG 6
SEG 7
SEG 8
NC
©
1995 Microchip Technology Inc.
SEG 18
SEG 17
SEG 16
SEG 15
SEG 14
SEG 13
SEG 12
SEG 11
SEG 10
SEG 9
NC
18
19
20
21
22
23
24
25
26
27
28
DS70010I-page 1
AY0438
FIGURE 1: PIN DESCRIPTIONS
Pin # (PDIP Only)
1
2
3-29, 32, 33, 37-39
30
31
34
35
36
40
Name
V
DD
Load
Seg 1-32
BP
LCD
Φ
Data In
Data Out
V
SS
Clock
Direction
-
Input
Output
Output
Input
Input
Output
Ground
Input
Description
Supply voltage
Latch data from registers
Direct drive outputs
Backplane drive output
Backplane drive input
Data input to shift register
Data output from shift register
Ground
System clock input
FIGURE 2: BLOCK DIAGRAM
Data in
Clock
Load
32-bit Static Shift Register
Data out
FIGURE 3: BACKPLANE AND SEGMENT
OUTPUT
32 Latches
SEG On
32 Segment Drivers
32 Outputs
Backplane
output
Backplane
LCDΦ
LCD AC
Generator
SEG Off
FIGURE 4: TIMING DIAGRAM
1/f
CLOCK
START
Data in
SEG 32
SEG 2
t
DS
Data out
t
PD
Load
t
PW
SEG 1
t
DH
1
31
32
1.0
1.1
OPERATION:
Data In and Clock
enabled or visible, i.e. the output at Segment Output is
180° out-of-phase with the Backplane output
(Figure 3).
The shift register shifts and outputs on the falling edge
of the clock. Every clock falling edge does a logical left
shift. As an example, if 32 clock pulses are supplied as
in Figure 4, then the data input at the first clock will out-
put at SEG 32, and the last data input (# 32) will output
at SEG 1 when a LOAD signal is enabled (Figure 2). It
is recommended that a complete 32 bit transfer be
done every time the outputs are updated. A logic 1 at
the Data In causes the corresponding segment to be
1.2
Load
A logic 1 at the Load input (Figure 2) causes the paral-
lel load of the data in the shift register into the latches
that control the segment drivers. If the Load signal is
tied high, then the latches become transparent and the
segment drivers are always connected to the shift reg-
isters.
DS70010I-page 2
©
1995 Microchip Technology Inc.
AY0438
1.3
LCD
φ
LCD
φ
can be driven by an external signal or by con-
necting a capacitor between LCD
φ
and ground (GND),
which will enable the on-chip oscillator required to gen-
erate the backplane output voltage. Figure 5 shows the
relationship between capacitance value and output fre-
quency. Leaving the LCDφ input unconnected is not
recommended. When driven by an external clock, the
backplane output is in phase with the input clock. When
cascading two AY0438 devices (Figure 6 and
Figure 7), the backplane output can be generated
using a capacitor to GND on the first AY0438. This
backplane output can then be connected to the LCDφ
input of the second AY0438. The backplane output of
the second device is then used to drive the backplane
of the LCD module.
FIGURE 5: OSCILLATOR FREQUENCY
GRAPH (TYPICAL @ 25
°
C)
140
Backplane Frequency (Hz)
120
100
80
60
40
0
20
40
60
CL (pF)
80
100
120
FIGURE 6: CASCADING TWO AY0438 DEVICES
Data
in
Data
out
Data
in Clock
Load
Clock
Load
32-bit Static Shift Register
32-bit Static Shift Register
Data
out
32 Latches
32 Latches
32 Segment Drivers
LCDΦ
1 to 32
Outputs
Backplane
output
LCDΦ
32 Segment Drivers
33 to 64
Outputs
Backplane
output
LCD AC
Generator
LCD AC
Generator
Clock
Load
FIGURE 7: CASCADE TIMING DIAGRAM
1/f
CLOCK
START
Data in
SEG 64
SEG 2
t
DS
Data out
t
PD
Load
t
PW
SEG 1
t
DH
1
63
64
©
1995 Microchip Technology Inc.
DS70010I-page 3
AY0438
1.4
General
1.5
In order to avoid any race conditions, the Data In and
Load signals should not be changed during a falling
edge of the Clock. Figure 4 and Figure 7 show a typical
timing diagram for a 32 segment and 64 segment LCD
module.
Interfacing to a LCD Module and
PIC16CXX Device
Figure 8 shows a typical layout of an AY0438 con-
nected to a LCD module and interfaced to a PIC16CXX
family device. Example 1 lists code used to program
the PIC16CXX device. This code was complied using
MPASM.
FIGURE 8: INTERFACING TO A LCD MODULE AND PIC16CXX DEVICE
AY0438
SEG1
SEG7
SEG6
SEG5
SEG A
SEG F
SEG G
SEG E
SEG D
SEG C
SEG B
A
F G B
C
E
D
LCD
Backplane
PIC16CXX
RB0
RB1
RB2
Clock
Data In
Load
SEG4
SEG3
SEG2
SEG9-15
SEG19-23
SEG25-31
7
7
7
RB7
LCDΦ
Backplane
EXAMPLE 1:
EXAMPLE CODE
;*************************************************************************
;This program shows an interface between a PIC16CXX device
;and the AY0438 LCD controller to control a 7 Segment
;4 digit LCD module.
;The PIC16CXX interface to the AY0438 Hardware:
;
;
PORTB bit 0 --> CLK
;
PORTB bit 1 --> DATA IN
;
PORTB bit 2 --> LOAD
;
;The LCD module is connected to the AY0438 as follows:
;
Most Significant digit --> seg1 to seg7
;
3rd Significant digit
--> seg9 to seg15
;
2nd Significant digit
--> seg17 to seg 23
;
Least Significant digit --> seg25 to seg 31
;
DS70010I-page 4
©
1995 Microchip Technology Inc.
AY0438
;The DP are not connected, but can be connected to seg8, 16, 24 & 32.
;For each digit, the segments are connected as:
;
Seg A --> seg(8*n + 1)
;
Seg B --> seg(8*n + 2)
;
Seg C --> seg(8*n + 3)
;
Seg D --> seg(8*n + 4)
;
Seg E --> seg(8*n + 5)
;
Seg F --> seg(8*n + 6)
;
Seg G --> seg(8*n + 7)
;where n = 0, 1, 2 and 3 for MSD, 3rdSD, 2ndSD and LSD respectively.
;The firmware uses the values in registers:
;
MSD, THRDSD, SCNDSD and LSD
to determine the values to be
;pulsed to the AY0438.
;In this example, a pushbutton connected to PORTB bit 7
;is checked periodically to see if it has been pressed. If so,
;the LCD values in locations MSD to LSD are updated.
;*************************************************************************
list p=16c71,f=inhx8m
;
;
MSD
equ
0x20
THRDSD equ
0x21
SCNDSD equ
0x22
LSD
equ
0x23
count
equ
0x24
temp
equ
0x25
PORTB
equ
0x06
#define CLK
PORTB,0
#define DATAIN PORTB,1
#define LOAD
PORTB,2
#define UPDATELCD PORTB,7
w
equ
0
STATUS equ
0x03
C
equ
0
RP0
equ
5
OPTION equ
0x81
RBPU
equ
7
PCL
equ
0x02
PCLATH equ
0x0A
;
;
org
0
goto
start
org
0x10
;
;This DecodeValue table must reside in page 0 for this program to work
;
DecodeValue
addwf
PCL
retlw
B'00111111'
;decode for 0
retlw
B'00000110'
;decode for 1
retlw
B'01011011'
;decode for 2
retlw
B'01001111'
;decode for 3
retlw
B'01100110'
;decode for 4
retlw
B'01101101'
;decode for 5
©
1995 Microchip Technology Inc.
DS70010I-page 5
