FINAL
Am29F100
1 Megabit (128 K x 8-bit/64 K x 16-bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s
Single power supply operation
— 5.0 V
±
10% for read, erase, and program
operations
— Simplifies system-level power requirements
s
High performance
— 70 ns maximum access time
s
Low power consumption
— 20 mA typical active read current for byte mode
— 28 mA typical active read current for word mode
— 30 mA typical program/erase current
— 25
µA
typical standby current
s
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
one 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
one 32 Kword sectors (word mode)
— Any combination of sectors can be erased
— Supports full chip erase
s
Top or bottom boot block configurations
available
s
Sector protection
— Hardware-based feature that disables/re-
enables program and erase operations in any
combination of sectors
— Sector protection/unprotection can be
implemented using standard PROM
programming equipment
— Temporary Sector Unprotect feature allows in-
system code changes in protected sectors
s
Embedded Algorithms
— Embedded Erase algorithm automatically
pre-programs and erases the chip or any
combination of designated sector
— Embedded Program algorithm automatically
programs and verifies data at specified address
s
Minimum 100,000 program/erase cycles
guaranteed
s
Package options
— 44-pin SO
— 48-pin TSOP
s
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
s
Data# Polling and Toggle Bits
— Provides a software method of detecting
program or erase cycle completion
s
Ready/Busy pin (RY/BY#)
— Provides a hardware method for detecting
program or erase cycle completion
s
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
s
Hardware RESET# pin
— Hardware method of resetting the device to
reading array data
Publication#
18926
Rev:
C
Amendment/+2
Issue Date:
March 1998
GENERAL DESCRIPTION
The Am29F100 is a 1 Mbit, 5.0 Volt-only Flash memory
organized as 131,072 bytes or 65,536 words. The
Am29F100 is offered in 44-pin SO and 48-pin TSOP
packages. Word-wide data appears on DQ0-DQ15;
byte-wide data on DQ0-DQ7. The device is designed to
be programmed in-system with the standard system
5.0 Volt V
CC
supply. A 12.0 volt V
PP
is not required for
program or erase operations. The device can also be
programmed or erased in standard EPROM program-
mers.
The standard device offers access times of 70, 90,
120, and 150 ns, allowing high-speed microproces-
sors to operate without wait states. To eliminate bus
contention the device has separate chip enable
(CE#), write enable (WE#) and output enable (OE#)
controls.
The device requires only a
single 5.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state machine that controls
the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the pro-
gramming and erase operations. Reading data out of
the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This invokes the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This invokes the
Embedded Erase
algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed) be-
fore executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The
Erase Suspend
feature enables the system to put
erase on hold for any period of time to read data from,
or program data to, a sector that is not being erased.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is erased
when shipped from the factory.
The
hardware data protection
measures include a
low V
CC
detector automatically inhibits write operations
during power transitions. The
hardware sector pro-
tection
feature disables both program and erase oper-
ations in any combination of the sectors of memory,
and is implemented using standard EPROM program-
mers. The
temporary sector unprotect
feature allows
in-system changes to protected sectors.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the
standby mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
h i g h e st l e v e l s o f q u a l i ty, re l i a b il i ty, a n d c o s t
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of
hot electron injection.
2
Am29F100
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Option (V
CC
= 5.0 V
±
10%)
Max Access Time (ns)
CE# Access (ns)
OE# Access (ns)
-70
70
70
30
-90
90
90
35
Am29F100
-120
120
120
50
-150
150
150
55
Note:
See the AC Characteristics section for full specifications.
BLOCK DIAGRAM
DQ0
–
DQ15
RY/BY#
Buffer
V
CC
V
SS
RY/BY#
Erase Voltage
Generator
Input/Output
Buffers
WE#
BYTE#
RESET#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
STB
V
CC
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0–A15
A-1
18926C-1
Am29F100
3
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
Standard TSOP
18926C-2
NC
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Reverse TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
NC
A7
A6
A5
A4
A3
A2
A1
18926C-3
4
Am29F100
CONNECTION DIAGRAMS
NC
RY/BY#
NC
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
NC
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
SO
18926C-4
PIN CONFIGURATION
A0–A15
= 16 Addresses
DQ0–DQ14 = 15 Data Inputs/Outputs
LOGIC SYMBOL
16
DQ15/A-1 = DQ15 (Data Input/Output, word mode),
A-1 (LSB Address Input, byte mode)
CE#
OE#
WE#
BYTE#
RESET#
RY/BY#
V
CC
= Chip Enable
= Output Enable
= Write Enable
= Selects 8-bit or 16-bit mode
= Hardware Reset Pin, Active Low
= Ready/Busy Output
= +5.0 Volt Single Power Supply
(See Product Selector Guide for speed
options and voltage supply tolerances)
= Device Ground
= Pin Not Connected Internally
A0–A15
DQ0–DQ15
(A-1)
16 or 8
CE#
OE#
WE#
RESET#
BYTE#
RY/BY#
18926C-5
V
SS
NC
Am29F100
5
FPGA/CPLD
