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PRELIMINARY

Am29LV800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

Single power supply operation

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

— Regulated voltage range: 3.0 to 3.6 volt read

and write operations and for compatibility with

high performance 3.3 volt microprocessors

Manufactured on 0.35 µm process technology

— Compatible with 0.5 µm Am29LV800 device

High performance

— Full voltage range: access times as fast as 80 ns

— Regulated voltage range: access times as fast

as 70 ns

Ultra low power consumption (typical values at

5 MHz)

— 200 nA Automatic Sleep mode current

— 200 nA standby mode current

— 7 mA read current

— 15 mA program/erase current

Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

fifteen 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

fifteen 32 Kword sectors (word mode)

— Supports full chip erase

— Sector Protection features:

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

Sectors can be locked in-system or via

programming equipment

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

Unlock Bypass Program Command

— Reduces overall programming time when

issuing multiple program command sequences

Top or bottom boot block configurations

available

Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

Minimum 1,000,000 write cycle guarantee per

sector

Package option

— 48-ball FBGA

— 48-pin TSOP

— 44-pin SO

Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

Data# Polling and toggle bits

— Provides a software method of detecting

program or erase operation completion

Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

Erase Suspend/Erase Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Publication#

21490

Rev:

Amendment/+1

Issue Date:

March 1998

Refer to AMD’s Website (www.amd.com) for the latest information.

P R E L I M I N A R Y

GENERAL DESCRIPTION

The Am29LV800B is an 8 Mbit, 3.0 volt-only Flash

memory organized as 1,048,576 bytes or 524,288

words. The device is offered in 48-ball FBGA, 44-pin

SO, and 48-pin TSOP packages. The word-wide data

(x16) appears on DQ15–DQ0; the byte-wide (x8) data

appears on DQ7–DQ0. This device requires only a

single, 3.0 volt V

supply to perform read, program,

and erase operations. A standard EPROM pro-

grammer can also be used to program and erase the

device.

This device is manufactured using AMD’s 0.35 µm

process technology, and offers all the features and

benefits of the Am29LV800, which was manufactured

using 0.5 µm process technology. In addition, the

Am29LV800B features unlock bypass programming

and in-system sector protection/unprotection.

The standard device offers access times of 70, 80, 90

and 120 ns, allowing high speed microprocessors to

operate without wait states. To eliminate bus conten-

tion the device has separate chip enable (CE#), write

enable (WE#) and output enable (OE#) controls.

The device requires only a

single 3.0 volt power sup-

ply

for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard.

Com-

mands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the

Embedded

Program

algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The

Unlock Bypass

mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

Device erasure occurs by executing the erase command

sequence. This initiates the

Embedded Erase

algo-

rithm—an internal algorithm that automatically prepro-

grams the array (if it is not already programmed) before

executing the erase operation. During erase, the device

automatically times the erase pulse widths and verifies

proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle)

status bits.

After a program or erase cycle

has been completed, the device is ready to read array

data or accept another command.

The

sector erase architecture

allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection

measures include a low

detector that automatically inhibits write opera-

tions during power transitions. The

hardware sector

protection

feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via program-

ming equipment.

The

Erase Suspend

feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The

hardware RESET# pin

terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the

automatic sleep mode.

The system can also place the device into the

standby

mode.

Power consumption is greatly reduced in both

these modes.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within

a sector simultaneously via Fowler-Nordheim tun-

neling. The data is programmed using hot electron

injection.

Am29LV800B

P R E L I M I N A R Y

PRODUCT SELECTOR GUIDE

Family Part Number

Speed Options

Regulated Voltage Range: V

=3.0–3.6 V

Full Voltage Range: V

= 2.7–3.6 V

Max access time, ns (t

ACC

)

Max CE# access time, ns (t

)

Max OE# access time, ns (t

)

70R

120

Am29LV800B

Note:

See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

RY/BY#

RESET#

Erase Voltage

Generator

Input/Output

Buffers

Sector Switches

DQ0

–

DQ15 (A-1)

WE#

BYTE#

State

Control

Command

PGM Voltage

Generator

Chip Enable

Output Enable

Logic

STB

Data

Latch

CE#

OE#

STB

Detector

Timer

Address Latch

Y-Decoder

Y-Gating

X-Decoder

Cell Matrix

A0–A18

21490E-1

Am29LV800B

P R E L I M I N A R Y

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

WE#

RESET#

RY/BY#

A18

A17

Standard TSOP

A16

BYTE#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

CE#

A16

BYTE#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

CE#

Reverse TSOP

A15

A14

A13

A12

A11

A10

WE#

RESET#

RY/BY#

A18

A17

21490E-2

Am29LV800B

P R E L I M I N A R Y

CONNECTION DIAGRAMS

RY/BY#

A18

A17

CE#

OE#

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

RESET#

WE#

A10

A11

A12

A13

A14

A15

A16

BYTE#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

FBGA

Bump Side (Bottom) View

RY/BY#

WE#

A13

A17

RESET#

A12

A18

A10

A14

A11

A15

DQ0

DQ2

DQ5

DQ7

A16

CE#

DQ8

DQ10

DQ12

DQ14

OE#

DQ9

DQ11

DQ13

DQ1

DQ3

DQ4

DQ6

BYTE# DQ15/A-1

21490E-3

Am29LV800B