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Am7969-125JC

LINE RECEIVER, PQCC28

器件类别:模拟混合信号IC    驱动程序和接口   

厂商名称:AMD(超微)

厂商官网:http://www.amd.com

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
AMD(超微)
零件包装代码
QLCC
包装说明
QCCJ,
针数
28
Reach Compliance Code
unknow
ECCN代码
EAR99
输入特性
DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型
LINE RECEIVER
接口标准
GENERAL PURPOSE
JESD-30 代码
S-PQCC-J28
长度
11.5062 mm
功能数量
1
端子数量
28
最高工作温度
70 °C
最低工作温度
输出特性
TOTEM-POLE
输出极性
TRUE
封装主体材料
PLASTIC/EPOXY
封装代码
QCCJ
封装形状
SQUARE
封装形式
CHIP CARRIER
峰值回流温度(摄氏度)
NOT SPECIFIED
认证状态
Not Qualified
最大接收延迟
接收器位数
1
座面最大高度
4.572 mm
最大供电电压
5.5 V
最小供电电压
4.5 V
标称供电电压
5 V
表面贴装
YES
技术
BIPOLAR
温度等级
COMMERCIAL
端子形式
J BEND
端子节距
1.27 mm
端子位置
QUAD
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
11.5062 mm
文档预览
TAXIchip
TM
Integrated Circuits
Transparent Asynchronous
Transmitter/Receiver Interface
Am7968/Am7969-125
Am7968/Am7969-175
Data Sheet
and
Technical Manual
1994
©
1994 Advanced Micro Devices, Inc.
Advanced Micro Devices reserves the right to make changes in its products
without notice in order to improve design or performance characteristics.
This publication neither states nor implies any warranty of any kind, including but not limited to implied warrants of merchantability or fitness
for a particular application. AMD
®
assumes no responsibility for the use of any circuitry other than the circuitry in an AMD product.
The information in this publication is believed to be accurate in all respects at the time of publication, but is subject to change without notice.
AMD assumes no responsibility for any errors or omissions, and disclaims responsibility for any consequences resulting from the use of the
information included herein. Additionally, AMD assumes no responsibility for the functioning of undescribed features or parameters.
Trademarks
AMD and the AMD logo are registered trademarks of Advanced Micro Devices, Inc.
TAXIchip and TAXI are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
TABLE OF CONTENTS
Am7968/Am7969 TAXIchip Integrated Circuits
Am7968/Am7969
Am7968/Am7969
Chapter 1
Data Sheet
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Technical Manual
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
1.1 The Am7968 TAXI
TM
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
1.2 The Am7969 TAXI Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Using the TAXIchip Set
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.1 Data and Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.2 Operational Modes: Local, Cascade and Test . . . . . . . . . . . . . . . . . . . . . . . . 53
Data Encoding, Violation and Syncs
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Violation Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 TAXI PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation and Distribution
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 TAXI Transmitter Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 Local Mode Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 TAXI Receiver Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1 Cascade Mode Receivers (Am7969-125 only) . . . . . . . . . . . . . . . . . .
Interfacing with the Serial Media
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Very Short Link, DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Terminated, DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Terminated, AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Baseline Wander and the AC Coupling Capacitor . . . . . . . . . . . . . . . . . . . . .
5.5 Interfacing to Fiber Optic Transmitters/Receivers . . . . . . . . . . . . . . . . . . . . .
5.5.1 DC-Coupled TAXl-Fiber Optic Transceiver Interface . . . . . . . . . . . . .
5.5.2 AC-Coupled TAXl-Fiber Optic Transceiver Interface . . . . . . . . . . . . .
5.6 Interfacing to Coaxial Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7 Interfacing to Twisted-Pair Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Board Layout Considerations
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Printed Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.1 Rules for Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Layout using Fiber Optic Data Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
53
57
57
59
59
60
60
61
61
62
63
63
64
66
66
68
68
70
71
71
71
73
Chapter 2
Chapter 3
Chapter 4
Chapter 5
Chapter 6
Table of Contents
iii
AMD
Chapter 7
Cascade Mode Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Transmit Cascaded Data with a Single TAXI Transmitter . . . . . . . . . . . . . . .
7.2 Receivers In Cascade Mode: Connections (Am7969-125 only) . . . . . . . . . . .
7.3 Auto-Repeat Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.1 Receiver Connections in Auto-Repeat Configuration . . . . . . . . . . . . .
7.3.2 Timing Limitations of the Auto-Repeat Configuration . . . . . . . . . . . . .
7.4 Unbalanced Configuration (Am7968/Am7969-125 only) . . . . . . . . . . . . . . . .
Test Mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 Transmitter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Receiver Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 Timing Relationships in Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
76
79
81
81
84
85
86
87
89
89
Chapter 8
Appendix A Optical Components Manufacturers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Appendix B Error Detection Efficiency
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Appendix C TAXI TIPs
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
iv
Table of Contents
FINAL
Am7968/Am7969
TAXIchip
TM
Integrated Circuits
(Transparent Asynchronous Xmitter-Receiver Interface)
DISTINCTIVE CHARACTERISTICS
s
Parallel TTL bus interface
— Eight Data and four Command Pins
— or nine Data and three Command Pins
— or ten Data and two Command Pins
s
Transparent synchronous serial link
— +5 V ECL Serial I/O
AC or DC coupled
NRZI 4B/5B, 5B/6B encoding/decoding
s
Drive coaxial cable or twisted pair directly
s
s
s
s
s
s
s
Advanced
Micro
Devices
Easy interface with fiber optic data links
32–140 Mbps (4–17.5 Mbyte/s) data
throughput
Asynchronous input using STRB/ACK
Automatic MUX/DEMUX of Data and Command
Complete on-chip PLL, Crystal Oscillator
Single +5 V supply operation
28-pin PLCC or DIP or LCC
GENERAL DESCRIPTION
The Am7968 TAXIchip Transmitter and Am7969
TAXIchip Receiver Chipset is a general-purpose inter-
face for very high-speed (4–17.5 Mbyte/s, 40–175
Mbaud serially) point-to-point communications over co-
axial or fiber-optic media. The TAXIchip set emulates a
pseudo-parallel register. They load data into one side
and output it on the other, except in this case, the “other”
side is separated by a long serial link.
The speed of a TAXIchip system is adjustable over a
range of frequencies, with parallel bus transfer rates of
4 Mbyte/s at the low end, and up to 17.5 Mbyte/s at the
high end. The flexible bus interface scheme of the
TAXIchip set accepts bytes that are either 8, 9, or
10 bits wide. Byte transfers can be Data or Command
signaling.
BLOCK DIAGRAM
Am7968
Data
N
Strobe (STRB)
Acknowledge (ACK
X1
Oscillator
and
Clock Gen.
Encoder Latch
Strobe &
Acknowledge
Input Latch
Command
M
X2
Clock (CLK)
Data Mode Select (DMS)
Data Encoder
Test Serial In
(TSERIN)
Serial Interface
Shifter
Media
Interface
(SEROUT+) Serial Out +
(SEROUT–) Serial Out –
Test/Local Select (TLS)
Note:
N can be 8, 9, or 10 bits; total of N + M = 12.
07370F-1
Publication#
07370
Rev.
F
Issue Date:
April 1994
Amendment
/0
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