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Structure
Product Name
Device Name
Features
:
:
:
:
Silicon Monolithic Integrated Circuit
Power Driver For CD-ROM
BA5912BFP
•
•
•
•
•
•
•
•
Driver exclusively for the 2-ch BTL
Use of an HSOP25PIN power package can achieve downsizing of the set.
A wide dynamic range
Using an external mute terminal, the output current can be muted.
(CH1, CH2 independently muted.)
Muting both 2CHs will lead to the standby mode.
Three power supply systems provided.(PreVcc, CH1 PowVcc, CH2 PowVcc)
Two built-in general OP-AMPs installed.
A built-in thermal shutdown circuit installed.
ABSOLUTE MAXIMUM RATINGS (Ta=25°C)
Parameter
Power Supply Voltage
Power Dissipation
Operating Temperature
Range
Storage Temperature
Range
Symbol
Vcc
Pd
Topr
Tstg
Limits
13.5
1.45*1
-35 to 85
-55 to 150
Unit
V
W
°C
°C
*1 When mounted on the glass/epoxy board with the size: 70 mm×70 mm, the thickness: 1.6 mm, and
the rate of copper foil occupancy area: 3% or less.
Over Ta=25°C, derating at the rate of 11.6mW/°C.
RECOMMENDED OPERATING CONDITIONS (To determine a power supply voltage, the power
dissipation must be taken into consideration.)
Parameter
Pre-stage Power
Supply Voltage
Power-stage Power
Supply Voltage
Symbol
PreVcc
PowVcc
Limits
4.5 to 13.2
4.5 to PreVcc
Unit
V
V
This product has not been checked for the strategic materials (or service) defined in the Foreign
Exchange and Foreign Trade Control Low of Japan so that a verification work is required before
exporting it.
Not designed for radiation resistance.
REV. A
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ELECTRIC CHARACTERISTICS (Ta=25°C, Pre, Pow Vcc=5V, BIAS=2.5V, RL=8Ω, unless otherwise
noted.)
The items except Maximum Output Amplitude and Standby Circuit Current have the constant limit values
regardless of the voltage value of VREF.
Parameter
Consumption Current (at no
signal)
Standby Circuit Current
<Driver Part>
Output Offset Voltage
Maximum Output Amplitude
1
Maximum Output Amplitude
2
Closed Circuit Voltage Gain
Mute ON Voltage
Mute OFF Voltage
Vref Switching Voltage 1
Vref Switching Voltage 2
<OP-AMP Part>
Offset Voltage
Input Bias Current
High-level Output Voltage
Low-level Output Voltage
Output Driving Current Sink
Output Driving Current
Source
Slew Rate
VOFOP
IBOP
VOHOP
VOLOP
ISINK
ISOURCE
SROP
-5
-
4.00
-
10
10
-
0
-
4.36
0.74
50
40
1
5
300
-
1.1
-
-
-
MV
NA
V
V
MA
MA
V/µs
Vcc with 50Ω attached
GND with 50Ω attached
100KHz square wave, 4V
P-P
output
Voo
VOM1
VOM2
Gvc
VMON
VMOFF
VREF1
VREF2
-50
3.2
3.7
10.0
GND
2.0
GND
2.0
0
3.5
4.0
11.5
-
-
-
-
50
-
-
13.0
0.5
Vcc
0.5
Vcc
MV
V
V
DB
V
V
V
V
Pre Vcc=Pow Vcc
Pre Vcc > Pow Vcc+VF
REF1,2
≤
0.5V
Pre Vcc=12V, Pow Vcc=5V
REF1,2 > 2.0V
VIN=BIAS
±
0.5V
Symbol
Icc
Iscc
MIN.
-
-
TYP
9.0
0
MAX.
14.0
100
Unit
MA
µA
Condition
when no load applied, REF1,2
≥
2.0V
When no load applied, REF1,2
≤
0.5V
OUTLINE DIMENSIONS, SYMBOLS
Part Number
(UNIT: mm)
REV. A
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APPLICATION CIRCUIT DIAGRAM
When used at Pre Vcc > Pow Vcc + VF and in the standby mode, REF1 (PIN3) and REF2 (PIN12) must be
set to open, or 0.5V or less. When used with REF1 (PIN3) and REF2 (PIN12) shorted; or MUTE1 (PIN2)
and MUTE2 (PIN13) shorted, each microcomputer output must be able to supply a current of 300µA or so.
PIN NUMBERS, PIN NAMES
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
Pin Name
GND
MUTE1
REF1
Pow Vcc1
OUT１-
OUT1+
GND
OUT2+
OUT2-
Pow Vcc2
Pre Vcc
REF2
MUTE2
Description
Substrate GND
CH1 mute terminal
CH1Vref switching terminal
Pow Vcc(CH1)
CH1 negative output terminal
CH1 positive output terminal
Substrate GND
CH2 positive output terminal
CH2 negative output terminal
Pow Vcc(CH2)
Pre Vcc
CH2Vref switching terminal
CH2 mute terminal
* The positive or negative polarity on an output
terminal is determine by the input polarity.
No.
14
15
16
17
18
19
20
21
22
23
24
25
Pin Name
IN2’
IN2
OP1-OUT
OP1-IN-
OP-IN+
GND
BIAS
OP2-IN+
OP2-IN-
OP2-OUT
IN1
IN1’
Description
CH2 input terminal for gain
control
CH2 input terminal with gain
fixed
Operational amplifier 1 output
Operational amplifier 1- input
Operational amplifier 1+ input
Substrate GND
Bias input terminal
Operational amplifier 2+ input
Operational amplifier 2- input
Operational amplifier 2 output
CH1 input terminal with gain
fixed
CH1 input terminal for gain
control
REV. A
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CAUTIONS ON USE
(1) When the mute terminal voltage (at pin 2 and pin 13) is set to open or dropped to 0.5V (typ.) or less,
the output current (CH1, CH2) can be muted individually. Under conditions of normal use, the pin 2
and pin 13 should be pulled-up to 2.0V or above. Setting both mute terminals (pin 2 and pin 13) to
open, or 0.5V or less will automatically enter the standby mode.
(2) On the Bias terminal (pin 20), the applied voltage of 0.7V (typ.) or less will activate a mute function.
Under conditions of normal use, It should be set to 1.0V or above.
(3) When the power supply voltage drops to 3.5V (typ.) or less, the internal circuit will turn OFF and, when
recovering to 4.0V (Typ.) or above, the internal circuit will startup.
(4) Thermal shutdown (TSD), mute ON, bias terminal voltage drop, or power supply voltage drop will
activate the mute function, where only the driver part can be muted. While muting, the voltage at the
output terminal will equal to the internal bias voltage.
(5) When Pre Vcc=Pow Vcc, the Vref switching terminal must be set to open or 0.5V or less (internal bias
voltage=(Pow VCC - VF)/2); or, when Pre Vcc>Pow Vcc+VF, the Vref switching terminal must be pulled
up to 2.0V or above (internal bias voltage=Pow VCC/2).
(6) Even though a radiating fin is connected to the GND inside of the package, it must be connected to the
external GND.
(7) About absolute maximum ratings
Exceeding the absolute maximum ratings, such as the applied voltage or the operating temperature
range, may cause permanent device damage. As these cases cannot be limited to the broken short
mode or the open mode, if a special mode where the absolute maximum ratings may be exceeded is
assumed, it is recommended to take mechanical safety measures such as attaching fuses.
(8) About power supply lines
As a measure against the back current regenerated by a counter electromotive force of the motor, a
capacitor to be used as a regenerated-current path can be installed between the power supply and
GND and its capacitance value should be determined after careful check that any problems, for
example, a leak capacitance of the electrolytic capacitor at low temperature, are not found in various
characteristics.
(9) About GND potential
The electric potential of the GND terminal must be kept lowest in the circuitry at any operation states.
(10) About thermal design
With consideration of the power dissipation (Pd) under conditions of actual use, a thermal design
provided with an enough margin should be done.
(11) About operations in a strong electric field
When used in a strong electric field, note that a malfunction may occur.
(12) ASO
When using this IC, the output Tr. must be set not to exceed the values specified in the absolute
maximum ratings and ASO.
(13) Thermal shutdown circuit
This IC incorporates a thermal shutdown circuit (TSD circuit). When the chip temperature reaches the
value shown below, the coil output to the motor will be set to open.
The thermal shutdown circuit is designed only to shut off the IC from a thermal runaway and not
intended to protect or guarantee the entire IC functions.
Therefore, users cannot assume that the TSD circuit once activated can be used continuously in the
subsequent operations.
TSD ON Temperature
[°C] (typ.)
175
Hysteresis Temperature
[°C] (typ.)
25
(14) About earth wiring patterns
When a small signal GND and a large current GND are provided, it is recommended that the large
current GND pattern and the small signal GND pattern should be separated and grounded at a single
point of the reference point of the set in order to prevent the voltage of the small signal GND from being
affected by a voltage change caused by the resistance of the pattern wiring and the large current.
Make sure that the GND wiring patterns of the external components will not change, too.
REV. A
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(15)
This IC is a monolithic IC which has a P
+
isolations and P substrate to isolate elements each other.
This P layer and an N layer in each element form a PN junction to construct various parasitic
elements. Due to the IC structure, the parasitic elements are inevitably created by the potential
relationship.
Activation of the parasitic elements can cause interference between circuits and may result in a
malfunction or, consequently, a fatal damage. Therefore, make sure that the IC must not be used
under conditions that may activate the parasitic elements, for example, applying the lower voltage
than the ground level (GND, P substrate) to the input terminals.
In addition, do not apply the voltage to input terminals without applying the power supply voltage to
the IC. Also while applying the power supply voltage, the voltage of each input terminal must not
be over the power supply voltage, or within the guaranteed values in the electric characteristics.
REV. A
