Preliminary
Datasheet
BB506C
Built in Biasing Circuit MOS FET IC
UHF RF Amplifier
Features
•
Built in Biasing Circuit; To reduce using parts cost & PC board space.
•
High gain
PG = 24 dB typ. (f = 900 MHz)
•
Low noise
NF = 1.4 dB typ. (f = 900 MHz)
•
Low output capacitance
Coss = 1.1 pF typ. (f = 1 MHz)
•
Provide mini mold packages: CMPAK-4 (SOT-343mod)
R07DS0288EJ0300
Rev.3.00
Jan 10, 2014
Outline
RENESAS Package code: PTSP0004ZA-A
(Package name: CMPAK-4)
2
3
1
4
1. Source
2. Gate1
3. Gate2
4. Drain
Notes:
1. Marking is “FS-“.
2. BB506C is individual type number of RENESAS BBFET.
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate1 to source voltage
Gate2 to source voltage
Drain current
Channel power dissipation
Channel temperature
Storage temperature
Symbol
V
DS
V
G1S
V
G2S
I
D
Pch
Note3
Tch
Tstg
Ratings
6
+6
–0
+6
–0
30
250
150
–55 to +150
Unit
V
V
V
mA
mW
°C
°C
Notes: 3. Value on the glass epoxy board (50 mm
×
40 mm
×
1 mm).
R07DS0288EJ0300 Rev.3.00
Jan 10, 2014
Page 1 of 9
BB506C
Preliminary
Electrical Characteristics
(Ta = 25°C)
Item
Drain to source breakdown
voltage
Gate1 to source breakdown
voltage
Gate2 to source breakdown
voltage
Gate1 to source cutoff
current
Gate2 to source cutoff
current
Gate1 to source cutoff
voltage
Gate2 to source cutoff
voltage
Drain current
Forward transfer admittance
Input capacitance
Output capacitance
Power gain
Noise figure
Symbol
V
(BR)DSS
V
(BR)G1SS
V
(BR)G2SS
I
G1SS
I
G2SS
V
G1S(off)
V
G2S(off)
I
D(op)
|y
fs
|
C
iss
C
oss
PG
NF
Min
6
+6
+6
—
—
0.5
0.4
12
27
1.2
0.7
19
—
Typ
—
—
—
—
—
0.8
0.7
16
32
1.6
1.1
24
1.4
Max
—
—
—
+100
+100
1.1
1.0
20
38
2.0
1.5
29
2.1
Unit
V
V
V
nA
nA
V
V
mA
mS
pF
pF
dB
dB
Test Conditions
I
D
= 200
μA,
V
G1S
= V
G2S
= 0
I
G1
= +10
μA,
V
G2S
= V
DS
= 0
I
G2
= +10
μA,
V
G1S
= V
DS
= 0
V
G1S
= +5 V, V
G2S
= V
DS
= 0
V
G2S
= +5 V, V
G1S
= V
DS
= 0
V
DS
= 5 V, V
G2S
= 4 V, I
D
= 100
μA
V
DS
= 5 V, V
G1S
= 5 V, I
D
= 100
μA
V
DS
= 5 V, V
G1
= 5 V, V
G2S
= 4 V
R
G
= 100 kΩ
V
DS
= 5 V, V
G1
= 5 V, V
G2S
= 4 V
R
G
= 100 kΩ, f = 1 kHz
V
DS
= 5 V, V
G1
= 5 V, V
G2S
= 4 V
R
G
= 100 kΩ, f = 1 MHz
V
DS
= 5 V, V
G1
= 5V, V
G2S
= 4 V
R
G
= 100 kΩ, f = 900 MHz
Bias Circuit for Operating Items (I
D(op)
, |y
fs
|, Ciss, Coss, NF, PG)
V
G2
Gate 2
Gate 1
R
G
V
G1
Drain
A
I
D
Source
R07DS0288EJ0300 Rev.3.00
Jan 10, 2014
Page 2 of 9
BB506C
Preliminary
900 MHz Power Gain, Noise Figure Test Circuit
V
G1
V
G2
C4
C5
V
D
C6
R1
R2
C3
G2
R3
D
L3
RFC
Output
(
50
Ω)
L4
Input
(
50
Ω)
L1
L2
G1
S
C1
C2
C1, C2
C3
C4 to C6
R1
R2
R3
:
:
:
:
:
:
Variable Capacitor (10 pF MAX)
Disk Capacitor (1000 pF)
Air Capacitor (1000 pF)
100 kΩ
47 kΩ
4.7 kΩ
L1:
10
L2:
10
26
(φ1 mm Copper wire)
Unit : mm
8
21
L4:
29
3
L3:
18
10
7
7
RFC : f1 mm Copper wire with enamel 4 turns inside dia 6 mm
R07DS0288EJ0300 Rev.3.00
Jan 10, 2014
10
3
Page 3 of 9
BB506C
Preliminary
Main Characteristics
Maximum Channel Power Dissipation Curve
Channel Power Dissipation Pch* (mW)
400
25
Typical Output Characteristics
V
G2S
= 4 V
V
DS
= V
G1
20
82 kΩ
68 kΩ
300
I
D
(mA)
15
100 kΩ
120 kΩ
200
Drain Current
10
k
Ω
150 kΩ
100
5
R
G
80
=1
0
50
100
150
200
0
0
1
2
3
4
5
Ambient Temperature T
a
(°C)
* Value on the glass epoxy board (50 mm
×
40 mm
×
1 mm)
Drain to Source Voltage V
DS
(V)
Forward Transfer Admittance
vs. Gate1 Voltage
|y
fs
| (mS)
50
V
DS
= 5 V
V
G2S
=4 V
R
G
= 100 kΩ
f = 1 kHz
Drain Current vs. Gate1 Voltage
25
V
DS
= 5 V
V
G2S
= 4 V
R
G
= 100 kΩ
I
D
(mA)
20
40
Forward Transfer Admittance
4V
15
4V
3V
3V
2V
30
20
Drain Current
10
5
V
G2S
= 1 V
0
0
1
2
3
4
5
10 V
G2S
= 0
2V
1V
0
0
1
2
3
4
5
Gate1 Voltage V
G1
(V)
Gate1 Voltage V
G1
(V)
Drain Current vs. Gate Resistance
25
5
Input Capacitance vs.
Gate2 to Source Voltage
V
DS
= 5 V
V
G1
= 5 V
R
G
= 100 kΩ
f = 1 MHz
Input Capacitance Ciss (pF)
100
1000
Drain Current I
D
(mA)
20
4
15
3
10
5
V
DS
= V
G1
= 5 V
V
G2S
= 4 V
0
10
2
1
0
0
1
2
3
4
Gate Resistance R
G
(kΩ)
Gate2 to Source Voltage V
G2S
(V)
R07DS0288EJ0300 Rev.3.00
Jan 10, 2014
Page 4 of 9
BB506C
Power Gain vs. Gate Resistance
50
V
DS
= 5 V
V
G1
= 5 V
V
G2S
= 4 V
f = 900 MHz
Preliminary
Noise Figure vs. Gate Resistance
5
V
DS
= 5 V
V
G1
= 5 V
V
G2S
= 4 V
f = 900 MHz
Power Gain PG (dB)
NF (dB)
Noise Figure
40
4
30
3
20
2
10
1
0
10
0
100
1000
10
100
1000
Gate Resistance R
G
(kΩ)
Power Gain vs.
Gate2 to Source Voltage
25
5
Gate Resistance R
G
(kΩ)
Noise Figure vs.
Gate2 to Source Voltage
V
DS
= 5 V
V
G1
= 5 V
R
G
= 100 kΩ
f = 900 MHz
NF (dB)
Noise Figure
4
V
DS
= 5 V
V
G1
=5 V
R
G
= 100 kΩ
f = 900 MHz
1
2
3
Power Gain PG (dB)
20
4
15
3
2
10
5
1
0
0
1
2
3
4
Gate2 to Source Voltage V
G2S
(V)
Gain Reduction vs.
Gate2 to Source Voltage
40
V
DS
= 5 V
V
G1
= 5 V
R
G
= 100 kΩ
f = 900 MHz
Gate2 to Source Voltage
V
G2S
(V)
Gain Reduction GR (dB)
35
30
25
20
15
10
5
0
0
1
2
3
4
Gate2 to Source Voltage V
G2S
(V)
R07DS0288EJ0300 Rev.3.00
Jan 10, 2014
Page 5 of 9
