Datasheet
Simple design with built-in self-controlled cell balance features circuit
Cell Balance LSI of 4 to 6 Series Power
Storage Element Cells for Automotive
BD14000EFV-C
General Description
BD14000EFV is a LSI IC designed as a self-controlled
cell balancer. It has a built-in shunt-type power storage
element balancer function that can respond to 4 to 6
cells. All the functions necessary in a cell balancer are
built-in making power storage element cell balancing
possible only in this LSI.
This chip can be used for electric double layer
capacitors (EDLC) with cell detection voltage range of
2.4V to 3.1V and power storage capacitors which is
important for cell balancers with similar electrical
characteristics
It has a built-in multiple over-voltage detection function
and can also detect abnormal mode such as any
characteristic deterioration in cells.
Also, application-dependent operation can be set since
enable control is possible.
Key Specifications
Input Voltage Range：8.0V to 24.0V
Cell Voltage Detection Range：2.4V to 3.1V
Cell Voltage Detection Accuracy：③1％(Max. at
25°C)
Shunt Switch ON Resistance：1Ω(Typ.)
Operating Temp. Range
：-40°C
to +105°C
Package
HTSSOP-B30
W (Typ) x D (Typ) x H (Max)
10.00mm x 7.60mm x 1.00mm
Features
HTSSOP-B30
(Note1)
AEC-Q100 qualified
All EDLC cell balancer functions are integrated on
a single chip
Self- controlled EDLC balance function
Adopts shunt resistance method for simple
balancing
4 to 6 cell series connection ready
Multiple chip series connection is possible
Built-in over-voltage detection flag output
Detection voltage can be set
(Note1 : Grade2)
Typical Application Circuit
Applications
Renewable energy power storage for Automotive,
Production machinery, Building machinery, etc.
UPS and other devices that stabilizes power
supplies
Figure 1 Typical application circuit
〇Product
structure : Silicon monolithic integrated circuit
〇This
product has no designed protection against radioactive rays
.
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BD14000EFV-C
Pin Configuration
T
Datasheet
_
_
_
T
T
_
T
T
T
Figure 2 Pin Configuration
Pin Description
PIN No.
1
2
Symbol
C6
D6
Function
Positive (+) connection terminal
pin of cell 6
PIN No.
16
Symbol
C1
Function
Positive (+) connection terminal pin of
cell 1
Shunt switch connection terminal
Shunt switch connection terminal pin for
17
D1
pin for cell 6.
cell 1
Shunt switch connection terminal
Shunt switch connection terminal pin for
3
S6
18
S1
pin for cell 6.
cell 1
Positive (+) connection terminal
Analog ground (connect to (-) side of
4
C5
19
VSS
pin of cell 5
bottom cell)
Shunt switch connection terminal
5
D5
20
VSET2
Detection voltage setting input pin 2
pin for cell 5.
Shunt switch connection terminal
6
S5
21
VSET1
Detection voltage setting input pin 1
pin for cell 5.
Positive (+) connection terminal
7
C4
22
VSET0
Detection voltage setting input pin 0
pin of cell 4.
Shunt switch connection terminal
8
D4
OVLOSEL
23
Over-voltage detection setting input pin
pin for cell 4.
Shunt switch connection terminal
9
S4
24
TEST0
TEST terminal pin (connect to VSS)
pin for cell 4.
Positive (+) connection terminal
10
C3
25
ENIN
Enable signal input pin
pin of cell 3.
Shunt switch connection terminal
11
D3
VO_OK
26
Self-Check OK signal output pin
pin for cell 3.
Shunt switch connection terminal
12
S3
VO_OVLO2
27
Overvoltage flag output pin 2
pin for cell 3.
Positive (+) connection terminal
13
C2
28
VO_OVLO1
Overvoltage flag output pin 1
pin of cell 2
Shunt switch connection terminal
Regulator circuit output pin
14
D2
29
VREG
pin for cell 2.
(output capacitor : 1.0µF)
Shunt switch connection terminal
15
S2
30
VCC
Regulator circuit power input pin
pin for cell 2.
The back PAD is used for enhancing the radiation of heat. This PAD is needed to connect VSS.
TEST0 : This pin is used for ROHM internal test. This pin is needed to connect VSS for normal operation.
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BD14000EFV-C
Block Diagram
Datasheet
T
T
T
T
T
T
T
T
,
T
,
T
_
_
_
T
T
Figure 3 Block Diagram
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BD14000EFV-C
Description of Blocks
Datasheet
CONTROL block
1.
Cell voltage detection block
Setting the detection voltage is possible with cell balance voltage detection and two types of OVLO available
for each cell.
Additionally, protection detection error can be controlled by setting delays for each voltage detection.
2.
Detect control block
ON/OFF control is possible by setting the ENIN pin.
Additionally, cell detection voltages can be set via VSET0, 1, 2 and OVLOSEL pins.
REG block
This is used as a power block for the chip’s internal blocks.
This block can also be used as I/F power source of control input/output.
Shunt SW
Shunt Switch is used for the cell balancing function.
SWDET
SWDET detects if the drain pins (D1~D6) are normally changed to “L” when cell balance voltage is
detected as a self-check function
Flag output
2 types of OVLO are output from VO_OVLO1, 2. Self-check function is output from VO_OK.
Absolute Maximum Ratings (Ta = 25°C)
Parameter
Supply Voltage
VCC,VCn(n=6) to VSS
Supply Voltage
VCn to Vcn-1(n=2~6)
VC1 to VSS
VDn to Vsn (n=1~6)
Supply Voltage
VREG,ENIN,VO_OVLO1,VO_OVLO2,
VO_OK,OVLOSEL,VSET0,VSET1,
VSET2,TEST0 to VSS
Power Dissipation
Operating Temperature Range
Storage Temperature Range
1
Symbol
V1-1
Rating
-0.3 to 28
Unit
V
V2-1
-0.3 to 7
V
V2-2
-0.3 to 7
*1
V
Pd
Topr
Tstg
1.55
W
°C
°C
-40 to +105
-55 to 150
* This value is for ROHM standard board (1 layer 70x70x1.6mm) mounting. For temperatures above 25°C, use a 12.4mW/°C derating factor.
Caution:
Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in cases where the IC is
operated over the absolute maximum ratings.
Recommended Operating Conditions
(Ta= -40°C to +105°C)
Parameter
VCC Voltage
Symbol
VCC
Rating
8.0 to 24
Unit
V
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BD14000EFV-C
Electrical Characteristics
(Unless otherwise specified VCC=15V Ta=25°C)
Parameter
Circuit Current
VCC circuit current when ON
VCC circuit current when standby
Cn(n=1~6) pin circuit current
when ON
Cn(n=5,6) pin circuit current
when standby
Cn(n=1~4) pin circuit current
when standby
Cell Voltage Detection
Cell Balance Start Detection
Voltage Range
Cell Balance Start
Detection Accuracy1
Cell Balance Start
Detection Accuracy2
Over- Voltage Detection 1
Detection Voltage1
Over- Voltage Detection 1
Detection Voltage2
Over- Voltage Detection 1
Detection Accuracy
Over- Voltage Detection 2
Detection Voltage1
Over- Voltage Detection 2
Detection Voltage2
Over- Voltage Detection 2
Detection Accuracy
Built-in Oscillator Frequency
VREG
Output Voltage
VREG
3.6
4.3
5.0
V
Io=10mA
IVCC
ON
IVCC
ICN
OFF56
OFF
-
-
40
25
20
1
0
80
50
40
8
5
µA
µA
µA
µA
µA
Symbol
Min
Typ
Max
Unit
Datasheet
Conditions
ENIN=H
During cell balance start
voltage non-detection
ENIN=L
ENIN=H,Vcn-Vcn-1=2.5V
During cell balance start
voltage non-detection
ENIN=L, Vcn-Vcn-1=2.5V
ENIN=H,Vcn-Vcn-1=2.5V
VCB
VCB
ERR1
VCB
ERR2
VOVLO
1-1
VOVLO
1-2
VOVLO1
ERR
VOVLO2
-1
VOVLO2
-2
VOVLO2
ERR
fosc
2.4
－
－
－
－
－
－
－
－
20
－
－
－
VCB
+0.15
VCB
+0.25
－
VCB
+0.3
VCB
+0.5
－
40
3.1
③1
③2
－
－
③2
－
－
③2
80
V
%
%
V
V
%
V
V
%
kHz
Set by VSET0½2 pin
Ta=-40½105°C
Set by VSET0½2 pin
and OVLOSEL=L
Set by VSET0½2 pin
and OVLOSEL=H
Ta=-40½105°C
Set by VSET0½2 pin
and OVLOSEL=L
Set by VSET0½2 pin
and OVLOSEL=H
Ta=-40½105°C
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