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BD3512MUV-E2

LDO Voltage Regulators LDO REG 0.65V-2.7V 3A 20PIN

器件类别:电源/电源管理    电源电路   

厂商名称:ROHM(罗姆半导体)

厂商官网:https://www.rohm.com/

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器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
零件包装代码
QFN
包装说明
QCCN, LCC20,.16SQ,20
针数
20
Reach Compliance Code
compliant
ECCN代码
EAR99
Factory Lead Time
8 weeks
Is Samacsys
N
可调性
ADJUSTABLE
标称回动电压 1
0.85 V
JESD-30 代码
S-XQCC-N20
最大电网调整率 (%/V)
0.5
最大负载调整率 (%)
1.5%
输出次数
1
端子数量
20
工作温度TJ-Max
100 °C
工作温度TJ-Min
-10 °C
最大输出电流 1
3 A
最大输出电压 1
2.7 V
最小输出电压 1
0.65 V
封装主体材料
UNSPECIFIED
封装代码
QCCN
封装等效代码
LCC20,.16SQ,20
封装形状
SQUARE
封装形式
CHIP CARRIER
包装方法
TAPE AND REEL
峰值回流温度(摄氏度)
NOT SPECIFIED
认证状态
Not Qualified
调节器类型
FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR
表面贴装
YES
技术
CMOS
端子形式
NO LEAD
端子节距
0.5 mm
端子位置
QUAD
处于峰值回流温度下的最长时间
NOT SPECIFIED
Base Number Matches
1
文档预览
Datasheet
0.7V to V
CC
-1V, 3A 1ch
Ultra-Low Dropout Linear Regulator
BD3512MUV
General Description
BD3512MUV is an ultra-low dropout linear chipset
regulator, which operates at a very low input supply. It
offers ideal performance in low input to output voltage
applications. The input-to-output voltage difference is
minimized by using a built-in N-Channel power
MOSFET with a maximum ON-Resistance of
R
ON
=100mΩ. By lowering the dropout voltage, the
regulator achieves high output current of up to
I
OUTMAX
=3.0A, thereby, reducing conversion loss, making
it comparable to a switching regulator and its power
transistor, choke coil, and rectifier diode constituents. It
is a low-cost design and is available in significantly
downsized package profiles. An external resistor sets
the output voltage which ranges from 0.65V to 2.7V,
while the NRCS (soft start) function enables a controlled
output voltage ramp-up, which can be programmed to
anything the power supply sequence is required.
Key Specifications
IN Input Voltage Range:
VCC Input Voltage Range:
Output Voltage Range:
Output Current:
ON-Resistance:
Standby Current:
Operating Temperature:
0.7V to V
CC
-1V
4.3V to 5.5V
0.65V to 2.7V
3.0A (Max)
65mΩ(Typ)
0μA (Typ)
-10°C to +100°C
Package
W(Typ) x D(Typ) x H(Max)
Features
Incorporates High-Precision Reference Voltage
Circuit (0.65V±1%)
Built-in VCC Undervoltage Lockout Circuit
(V
CC
=3.80V)
NRCS (Soft-start) Function Reduces the
Magnitude of In-rush Current
Built-in N-Channel MOSFET
Built-in Current Limit Circuit (3.0A min)
Built-in Thermal Shutdown (TSD) Circuit (Timer
latch)
Tracking Function
VQFN020V4040
4.00mm x 4.00mm x 1.00mm
Applications
Notebook and Desktop computers, LCD-TV, DVD,
Digital appliances
Typical Application Circuit and Block Diagram
VCC
C
1
VCC
6
UVLO2
V
CC
EN
UVLO1
UVLO1
V
CC
VREF
NRCS
OUT
14
SCP/TSD
LATCH
LATCH
8
V
IN
UVLOLATCH
V
CC
CL
Current
Limit
VD
IN
9
VREF
X 0.7
10
EN
7
IN
Reference
Block
11
12
13
R
1
R
2
C
2
NRCS x 0.3
VREF x 0.4
FB
SCP
2
C
SCP
TSD
EN
UVLO1
CL
UVLO1
UVLO2
TSD
SCP
EN
15
16
17
18
R
2
C
FB
OUT
C
3
19
FB
NRCS
20
C
NRCS
EN/UVLO
NRCS
POWER
GOOD
R
1
5
VDD
3
PGDLY
1
4
GND
PG
○Product
structure:Silicon monolithic integrated circuit
www.rohm.com
© 2015 ROHM Co., Ltd. All rights reserved.
TSZ22111・14・001
○This
product has no designed protection against radioactive rays
1/23
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
BD3512MUV
Pin Configuration
Pin Descriptions
Pin No.
1
IN4
12
IN3
11
10 IN2
9
FIN
OUT 5
18
8
7
6
1
2
3
4
5
VDD
VD
EN
VCC
IN1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
bottom
Pin Name
GND1
SCP
PGDLY
PG
VDD
VCC
EN
VD
IN1
IN2
IN3
IN4
IN5
OUT1
OUT 2
OUT 3
OUT 4
OUT 5
FB
NRCS
FIN
PIN Function
Ground pin 1
SCP delay time setting capacitor
connection pin
PGOOD delay setting
capacitor connection pin
Power good pin
Power supply pin
Power supply pin
Enable input pin
IN input voltage detect pin
Input voltage pin 1
Input voltage pin 2
Input voltage pin 3
Input voltage pin 4
Input voltage pin 5
Output voltage pin 1
Output voltage pin 2
Output voltage pin 3
Output voltage pin 4
Output voltage pin 5
Reference voltage feedback pin
In-rush current protection (NRCS)
capacitor connection pin
Connected to heat sink and GND
TOP VIEW
OUT2 OUT1
15
OUT3 16
OUT 4
17
14
IN5
13
FB 19
NRCS
20
GND1 SCP PGDLY PG
(Note) Please short N.C to the GND line.
Description of Blocks
1. AMP
This is an error amplifier, which compares the reference voltage (0.65V) to FB voltage to drive the output N-Channel FET.
Frequency optimization aids in attaining rapid transient response, and to support the use of ceramic capacitors on the
output. AMP output voltage ranges from GND to VCC. When EN is OFF, or when UVLO is active, output goes LOW and
the output of the N-Channel FET switches to OFF state.
2. EN
The EN block controls the ON and OFF state of the regulator via the EN logic input pin. During OFF state, circuit voltage
stabilizes at 0μA which minimizes the current consumption during standby mode. The FET is switched ON to enable the
discharge of NRCS and OUT, thereby draining the excess charge and preventing the load side of an IC from
malfunctioning. Since there is no electrical connection required (e.g. between the VCC pin and the ESD prevention
diode), module operation is independent of the input sequence.
3. UVLO
To prevent malfunctions that can occur during sudden decrease in VCC, the UVLO circuit switches the output to OFF
state, and (like the EN block) discharges NRCS and OUT. Once the UVLO threshold voltage (TYP3.80V) is reached, the
power-ON reset is triggered and the output is restored.
4. CURRENT LIMIT
During ON state, it monitors the output current of the IC against the current limit value. When the output current exceeds
this value, this block lowers the output current to protect the load of the IC. When it overcomes the overcurrent state,
output voltage is restored to allowable value.
5. NRCS (Non Rush Current on Start-up)
The soft start function is enabled by connecting an external capacitor between the NRCS pin and ground. Output
ramp-up can be set to any period up to the time the NRCS pin reaches V
FB
(0.65V). During startup, the NRCS pin serves
as a constant current source about 20μA (TYP) to charge the external capacitor. Capacitors with low susceptibility
(0.001µF to 1µF) to temperature are recommended, in order to assure a stable soft-start time.
www.rohm.com
© 2015 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
2/23
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
BD3512MUV
Description of Blocks –continued
6. TSD (Thermal Shut down)
The shutdown (TSD) circuit is automatically latched OFF when the chip temperature exceeds the threshold temperature
after the programmed time period elapses, thus protecting the IC against “thermal runaway” and heat damage. Since the
TSD circuit is designed only to shut down the IC in the occurrence of extreme heat, it is important that the Tj(max)
parameter should not be exceeded in the thermal design, in order to avoid potential problems with the TSD.
7. IN
The IN line acts as the major current supply line, and is connected to the output N-Channel FET drain. Since there is no
electrical connection (such as between the VCC pin and the ESD protection diode) required, IN operates independent of
the input sequence. However, since an output N-Channel FET body diode exists between IN and OUT, a V
IN
-V
OUT
electric (diode) connection is present. Therefore, when output is switched ON or OFF, reverse current may flow from
OUT to IN.
8. PGOOD
It determines the status of the output voltage. This is an open-drain pin, which is connected to VCC pin through the
pull-up resistance (100kΩ or so). When the output voltage ranges from V
OUT
x 0.9 to V
OUT
x 1.1(TYP), the status is high.
Absolute Maximum Ratings
(Ta=25°C)
Parameter
Input Voltage 1
Input Voltage 2
Input Voltage 3
Input Voltage 4
Maximum Output Current
Enable Input Voltage
PGOOD Input Voltage
Power Dissipation 1
Power Dissipation 2
Power Dissipation 3
Power Dissipation 4
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Symbol
V
CC
V
IN
V
DD
V
VD
I
OUT
V
EN
V
PGOOD
Pd1
Pd2
Pd3
Pd4
Topr
Tstg
Tjmax
Limit
6.0
(Note 1)
6.0
(Note 1)
6.0
(Note 1)
1
3
(Note 1)
6.0
6.0
0.34
(Note 2)
0.70
(Note 3)
2.21
(Note 4)
3.56
(Note 5)
-10 to +100
-55 to +125
+150
Unit
V
V
V
V
A
V
V
W
W
W
W
°C
°C
°C
(Note 1) Should not exceed Pd.
(Note 2) Derating in done 2.7mV/°C for operating above Ta ≥ 25°C no heat sink
(Note 3) Derating in done 5.6mV/°C for operating above Ta ≥ 25°C
PCB size:74.2mm x 74.2mm x 1.6mm when mounted on a 1-layer glass epoxy board(copper foil area : 10.29mm
2
)
(Note 4) Derating in done 17.7mV/°C for operating above Ta ≥ 25°C
PCB size:74.2mm x 74.2mm x 1.6mm when mounted on a 4-layer glass epoxy board(copper foil area : front and reverse 10.29mm
2
, 2nd and 3rd
5505mm
2
)
(Note 5) Derating in done 28.5mV/°C for operating above Ta ≥ 25°C
PCB size:74.2mm x 74.2mm x 1.6mm when mounted on a 4-layer glass epoxy board(copper foil area : each 5505mm
2
)
Caution:
Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over
the absolute maximum ratings.
Recommended Operating Conditions
(Ta=25°C)
Parameter
Input Voltage 1
Input Voltage 2
Input Voltage 3
Output Voltage Setting Range
Enable Input Voltage
Symbol
V
CC
V
IN
V
DD
V
OUT
V
EN
Min
4.3
0.7
4.5
V
FB
-0.3
Max
5.5
V
CC
-1
(Note 6)
5.5
2.7
+5.5
Unit
V
V
V
V
V
(Note 6) VCC and IN do not have to be implemented in the order listed.
www.rohm.com
© 2015 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
3/23
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
BD3512MUV
Electrical Characteristics
(Unless otherwise specified, Ta=25°C, V
CC
=5V, V
EN
=3V, V
IN
=1.7V, R
1
=3.9kΩ, R
2
=3.3kΩ)
Parameter
Circuit Current
VCC Shutdown Mode Current
Maximum Output Current
Output Voltage Temperature
Coefficient
Feedback Voltage 1
Feedback Voltage 2
Line Regulation 1
Line Regulation 2
Load Regulation
Minimum dropout voltage
Standby Discharge Current
[ENABLE]
Enable Pin
Input Voltage High
Enable Pin
Input Voltage Low
Enable Input Bias Current
[FEEDBACK]
Feedback Pin Bias Current
[NRCS]
NRCS Charge Current
NRCS Standby Voltage
[UVLO]
VCC Undervoltage Lockout
Threshold Voltage
VCC Undervoltage Lockout
Hysteresis Voltage
VD Undervoltage Lockout
Threshold Voltage
[SCP]
SCP Startup Voltage
SCP Threshold Voltage
SCP Charge Current
SCP Standby Voltage
[PGOOD]
Low-side Threshold Voltage
High-side Threshold Voltage
PGDLY Charge Current
Ron
t
PGDLY
½
C
pF
1.23
sec
I
PGDLY
A
Symbol
I
CC
I
ST
I
OUT
Tcvo
V
FB1
V
FB2
Reg.l1
Reg.l2
Reg.L
dVo
I
DEN
V
ENHI
V
ENLOW
I
EN
I
FB
I
NRCS
V
STB
Min
-
-
3.0
-
0.643
0.637
-
-
-
-
1
2
-0.2
-
-100
14
-
Limit
Typ
1.4
0
-
0.01
0.650
0.650
0.1
0.1
0.5
65
-
-
-
6
0
20
0
Max
2.2
10
-
-
0.657
0.663
0.5
0.5
10
100
-
-
+0.8
10
+100
26
50
Unit
mA
µA
A
%/°C
V
V
%/V
%/V
mV
mV
mA
V
V
µA
nA
µA
mV
V
EN
=3V
Conditions
V
EN
=0V
I
OUT
=0A to 3A
Tj=-10°C to +100°C
V
CC
=4.3V to 5.5V
V
IN
=1.5V to 3.3V
I
OUT
=0A to 3A
I
OUT
=1A,V
IN
=1.2V
V
EN
=0V, V
OUT
=1V
V
NRCS
=0.5V
V
EN
=0V
V
CCUVLO
V
CCHYS
V
DUVLO
3.5
100
3.8
160
4.1
220
V
mV
V
VCC: Sweep-up
VCC: Sweep-down
VD: Sweep-up
V
REF
x 0.6 V
REF
x 0.7 V
REF
x 0.8
V
OUTSCP
V
OUT
x 0.3 V
OUT
x 0.4 V
OUT
x 0.5
V
SCPTH
1.05
1.15
1.25
I
SCP
1.4
2
2.6
V
SCPSTBY
-
-
50
V
OUT
x
0.87
V
OUT
x
1.07
1.4
-
V
V
µA
mV
V
THPGL
V
THPGH
I
PGDLY
R
PG
V
OUT
x 0.9 V
OUT
x 0.93
V
OUT
x 1.1 V
OUT
x 1.13
2.0
0.1
2.6
-
V
V
µA
(Note)
(Note) PGOOD delay time is determined using the formula below:
www.rohm.com
© 2015 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
4/23
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
BD3512MUV
Typical Waveforms
V
OUT
50mV/div
V
OUT
50mV/div
I
OUT
1A/div
3.0A
I
OUT
1A/div
3.0A
I
OUT
=0A to 3A/3µsec
t(10µsec/div)
I
OUT
=0A to 3A/3µsec
t(4µsec/div)
Figure 1. Transient Response
(0A to 3A)
C
OUT
=22μF, C
FB
=1000pF
Figure 2. Transient Response
(0A to 3A)
C
OUT
=100μF
V
OUT
50mV/div
V
OUT
50mV/div
I
OUT
1A/div
3.0A
I
OUT
1A/div
3.0A
I
OUT
=0A to 3A/3µsec
t(4µsec/div)
I
OUT
=3A to 0A/3µsec
t(40µsec/div)
Figure 3. Transient Response
(0A to 3A)
C
OUT
=100μF, C
FB
=1000pF
Figure 4. Transient Response
(3A to 0A)
C
OUT
=22μF, C
FB
=1000pF
www.rohm.com
© 2015 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
5/23
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
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