Power Supply IC Series for TFT LCD Panels
High-precision
Gamma Correction IC with built-in DAC
BD8143MUV
No.09035EBT08
●Description
This gamma correction voltage generation IC feature built-in DACs and provide a 1chip solution with setting control via serial
communications, a high-precision 10-bitDAC, and Buffer Amp (12ch).
●Features
1) 1chip design means fewer components
2) Built-in 10bit DAC
3) DAC output Buffer AMP (12ch)
4) Amp input select (CTL)
5) 3-line serial interface control
6) Thermal shut down
7) Power ON Reset Circuit
8) VQFN032V5050 Package
●Applications
These ICs can be used with TFT LCD Panels used by Large-Screen and High-Definition LCD TVs.
●Absolute
maximum ratings (Ta=25℃)
Parameter
Power Supply Voltage 1
Power Supply Voltage 2
REFIN Voltage
Symbol
DVCC
VCC
REF
Io
Tjmax
Pd
Topr
Tstg
Limit
7
20
20
30 *
1
Unit
V
V
V
mA
℃
mW
℃
℃
Amplifier Drive Current
Junction Temperature
Power Dissipation
Operating Temperature Range
Storage Temperature Range
150
2440 *
2
-40½+105
-55½+150
*1 Pd, should not be exceeded.
*2 Reduced by 19.52mW/°C over 25°C, when mounted on a glass epoxy board.
(4-layer 74.2×74.2×1.6mm).
●Operating
Condition (Ta=-40℃½105℃)
Parameter
Power Supply Voltage 1
Power Supply Voltage 2
REFIN Voltage
AMP0 Drive Current
AMP1½10 Drive Current
AMP11 Drive Current
Serial CLK Frequency
OSC Frequency
Symbol
DVCC
VCC
REF
I
OA
I
OB
I
OC
fCLK
F
OSC
Limit
MIN
2.3
8
8
-40
-20
-
-
-
MAX
5.5
18
18
-
20
40
5
200
Unit
V
V
V
mA
mA
mA
MHz
kHz
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© 2009 ROHM Co., Ltd. All rights reserved.
1/10
2009.07 - Rev.B
BD8143MUV
●Electrical
Characteristics (Unless otherwise specified, Ta=25℃,DVCC=3.3V,VCC=15V)
Limit
Parameter
Symbol
Unit
MIN
TYP
MAX
〔REFIN〕
Sink Current
Iref
90
200
µA
〔γCORRECTION
AMP〕
Source Drive Current (AMP0)
IooA
-60
mA
Source Drive Current (AMP1½10)
IooB
-30
mA
Source Drive Current (AMP11)
IooC
-10
mA
Sink Drive Current (AMP0)
IoiA
10
mA
Sink Drive Current (AMP1½10)
IoiB
30
mA
Sink Drive Current (AMP11)
IoiC
60
mA
Load regulation (OUT0)
⊿V-A
10
mV
Load regulation (OUT1½10)
⊿V-B
10
mV
Load regulation (OUT11)
⊿V-C
10
mV
Slew Rate
SR
3
V/µs
OUT Voltage High (OUT0)
VOH-A
VCC-0.4
VCC-0.15
-
V
OUT Voltage High (OUT1½10)
VOH-B
VCC-0.75
-
V
OUT Voltage High (OUT11)
VOH-C
VCC-0.75
-
V
OUT Voltage Low (OUT0)
VOL-A
-
0.75
V
OUT Voltage Low (OUT1½10)
VOL-B
-
0.75
V
OUT Voltage Low (OUT11)
VOL-C
-
0.1
0.2
V
〔DAC〕
Resolution Coding
Res
10
Bit
Non-Linear Error (INL)
Differential Error (DNL)
〔OSC〕
OSC Frequency
〔CONTROL
SIGNAL〕
Sink Current
Threshold Voltage
〔CONTROL〕
OUT0 Voltage
OUT1 Voltage
OUT2 Voltage
OUT3 Voltage
OUT4 Voltage
OUT5 Voltage
OUT6 Voltage
OUT7 Voltage
OUT8 Voltage
OUT9 Voltage
OUT10 Voltage
OUT11 Voltage
〔WHOLE
DEVICE〕
VDAC Detection Voltage
Circuit Current
LE
DLE
-2
-2
-
-
2
2
LSB
LSB
Technical Note
Conditions
REF=10V
DAC=7V,OUT0=13V
DAC=3.5V,OUT1½10=0V
DAC=0.5V,OUT11=0V
DAC=7V,OUT0=15V
DAC=3.5V,OUT1½10=15V
DAC=0.5V,OUT11=2V
Io=0mA½-35mA, OUTx=6V
Io=-15mA½15mA, OUTx=6V
Io=0mA½35mA, OUTx=6V
Io=-35mA
Io=-15mA
Io=-15mA
Io=15mA
Io=15mA
Io=35mA
Error with ideal straight Range
00A½3F5
Error with ideal amount of
Increase in 1LSB Range
00A½3F5
Internal oscillator mode
V
IN
=3.3V
fosc
Ictl
V
TH
Vpre0
Vpre1
Vpre2
Vpre3
Vpre4
Vpre5
Vpre6
Vpre7
Vpre8
Vpre9
Vpre10
Vpre11
Vdet
ICC
-
100
16.5
-
kHz
µA
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
DVCC×0.2
-
-
-
-
-
-
-
-
-
-
-
-
2.6
REFIN
X 12/13
REFIN
X 11/13
REFIN
X 10/13
REFIN
X 9/13
REFIN
X 813
REFIN
X 7/13
REFIN
X 6/13
REFIN
X 5/13
REFIN
X 4/13
REFIN
X 3/13
REFIN
X 2/13
REFIN
X 1/13
3.2
5
DVCC×0.8
-
-
-
-
-
-
-
-
-
-
-
-
3.6
CTL=”LOW”
CTL=”LOW”
CTL=”LOW”
CTL=”LOW”
CTL=”LOW”
CTL=”LOW”
CTL=”LOW”
CTL=”LOW”
CTL=”LOW”
CTL=”LOW”
CTL=”LOW”
CTL=”LOW”
CTL=”LOW”
This
product is not designed for protection against radio active rays.
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© 2009 ROHM Co., Ltd. All rights reserved.
2/10
2009.07 - Rev.B
BD8143MUV
●Pin
No
AGND
AGND
OUT5
OUT6
OUT7
OUT4
OUT3
OUT8
Technical Note
●Block
Diagram
VDD
VCC
VCC
REFIN
VDAC
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
R
VCC
VDAC
REG
REGISTER0
VDAC
VCC
AMP0
x2
OUT0
AMP1
OUT9
OUT10
OUT11
VCC
REFIN
VDAC
DACG ND
N.C
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
OUT2
OUT1
OUT0
VCC
N.C
CTL
N.C
OSC
LATCH
DATA
CLK
CT
VDD
R
REGISTER1
x2
OUT1
AMP2
REGISTER2
x2
OUT2
AMP3
REGISTER3
VREF
UVLO
TSD
REGISTER4
x2
OUT3
AMP4
x2
OUT4
AMP5
REGISTER5
x2
OUT5
AMP6
Power
ON
Reset
REGISTER6
DAC
Control
x2
OUT6
AMP7
REGISTER7
x2
OUT7
AMP8
Serial
I/F
REGISTER8
x2
OUT8
AMP9
REGISTER9
x2
OUT9
REGISTER10
x2
AMP10
OUT10
AMP11
SDOUT
VDD
REGISTER11
x2
OUT11
OSC
Refresh
Control
REGISTER12
CTL
CTL
SDOUT
DVCC
DACGND
GND
OSC
AGND
AGND
CLK
CT
LATCH
SDIN
GND
●Pin
NO. & Function Table
PIN
Pin
Function
No.
Name
1
LATCH
LATCH signal input
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SDIN
CLK
SDOUT
DVCC
CT
GND
N.C
OSC
N.C
CTL
N.C
VCC
OUT0
OUT1
OUT2
Gamma 0 output
Gamma 1 output
Gamma 2 output
DATA signal input
CLK signal input
DATA signal output
Digital Power Supply
Capacitor connection for Power on Reset
Ground
-
DAC Synchronized clock inout
-
Output control signal input
-
Power Supply for Buffer AMP
N.C
Fig.1 Pin No. & Block Diagram
PIN
No.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin
Name
OUT3
OUT4
OUT5
AGND
AGND
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
VCC
REFIN
VDAC
DACGND
N.C
Function
Gamma 3 output
Gamma 4 output
Gamma 5 output
Ground for Buffer AMP
Ground for Buffer AMP
Gamma 6 output
Gamma 7 output
Gamma 8 output
Gamma 9 output
Gamma 10 output
Gamma 11 output
Power Supply for Buffer AMP
DAC reference input
DAC Voltage output
Ground for DAC
-
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3/10
2009.07 - Rev.B
BD8143MUV
Technical Note
●Block
Operation
・REG
REG amplifiers the voltage applied to REFIN by 0.5x and output it to the VDAC pin. Connect a 1µF phase compensation
capacitor to the VDAC pin.
・DAC
Control
DAC Control convents the 10-bit digital signal read to the register to a voltage.
・Amp
Amp amplifiers the voltage output from DAC Control by 2x. Input includes sample & hold function, refreshed by OSC.
・OSC
The OSC generates the frequency that determines the Amp's refresh time.
External input can be selected using serial input.
・Power
On Reset
When the digital power supply DVCC is activated, each IC generates a reset signal to initialize the serial interface, registers.
Adding a 1,000 pF capacitor to the CT pin ensures that reset operation can be performed reliably, without regard to the
speed with which the power supply starts up.
・VREF
This block generates the internal reference voltage.
・TSD(Thermal
Shut Down)
The TSD circuit turns output off when the chip temperature reaches or exceeds approximately 175°C(TYP) in order to
prevent thermal destruction or thermal runaway. When the chip returns to a specified temperature, the circuit resets.
The TSD circuit is designed only to protect the IC itself. Application thermal design should ensure operation of the IC
below the thermal shutdown junction temperature of approximately 150°C(TYP).
・CTL
CTL signal can select Amp input. If CTL=”L”, each output voltage is fixed at REFIN voltage divided 13th equality.
IF CTL=”H”, each Amp input connect DAC output, and each output comply with each register.
・Register
A serial signal (consisting of 10-bit gamma correction voltage values) input using the serial interface is held for each
register address. Data is initialized by the reset signal generated during a power-on reset.
・Serial
I/F
The serial interface uses a 3-line serial data format (LATCH, CLK, SDIN). It is used to set gamma correction voltages,
specify register addresses, and select OSC I/O.
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4/10
2009.07 - Rev.B
BD8143MUV
Technical Note
●Serial
Communication
The serial data control block is composed of Shift-Register, DAC Register and DAC circuit.
The DAC register memorizes data from the serial interface (LATCH, CLK and SDIN).
The DAC circuit makes control voltage from the register output and it outputs to the each block. The DAC register value turns
back the preset value when Power Supply starts up.
Then, beginning 1bit of SDIN is always 0, because it is for test. Next 1bit switches OSC mode.
If input 0, OSC mode is internal mode (the frequency is 100kHz). If input 1, it is external one that require external clock.
SERIAL DATA CONTROL BLOCK
LATCH
CLK
SDIN
CLOCK
CONTROL
Shift Register
d16
d15
d14
d13
d12
d10
d11
d9
d8
d7
d6
d5
d4
d3
d2
d1
1bit
10bit
5bit
d0
1bit
OUT0½12
Register
ADDRESS
DECORDE
OSC
MODE
TEST
MODE
DAC
Fig.2 SERIAL BLOCK
①TIMING
OF SERIAL COMMUNICATION
The 17 bits Serial data from SDIN terminal is loaded to Shift-Register at the rise edge of CLK, and these data is loaded to
DAC Register at the rise edge of LATCH.
If serial data period is less than 17 bits while LATCH state is LOW, the serial data is not memorized. If serial data period is
more than 17 bits while LATCH state is LOW, last 17 bits are effective.
TIMING OF SERIAL COMMUNICATION
LATCH
CLK
SDIN
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9
d10 d1
1
d12 d13 d14 d15 d16
Fig.3 TIMING OF SERIAL COMMUNICATION
②SERIAL
DATA
The composition of SERIAL DATA INPUT(SDIN)
First
→
d0
d1
d2
d3
d4
d5
d6
0
X
Resister Address
ADDRESS
d2
0
0
0
0
0
0
0
0
0
0
0
0
0
d3
0
0
0
0
0
0
0
0
1
1
1
1
1
d4
0
0
0
0
1
1
1
1
0
0
0
0
1
d5
0
0
1
1
0
0
1
1
0
0
1
1
0
d6
0
1
0
1
0
1
0
1
0
1
0
1
0
d7
d8
d9
d10
d11
d12
d13
d14
→
Last
d15
d16
DATA
PRESET VALUE
d7½d16
00
00
00
00
00
00
00
00
00
00
00
00
00
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
REGISTER NAME
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12(*)
FUNCTION
OUT0 Voltage of control
OUT1 Voltage of control
OUT2 Voltage of control
OUT3 Voltage of control
OUT4 Voltage of control
OUT5 Voltage of control
OUT6 Voltage of control
OUT7 Voltage of control
OUT8 Voltage of control
OUT9 Voltage of control
OUT10 Voltage of control
OUT11 Voltage of control
-
(*)IF Register 12 is loaded at DATA=1010100000(2A0h), each output comply with each register regardless of CTL signal.
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5/10
2009.07 - Rev.B
Microchip MCU
