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STRUCTURE
NAME OF PRODUCT
TYPE
FUNCTION
Silicon Monolithic Integrated Circuit
DC-AC Inverter Control IC
ＢＤ９８８９ＦＶ
・2ch control with Push-Pull
・Lamp current and voltage sense feed back control
・Sequencing easily achieved with Soft Start Control
・Short circuit protection with Timer Latch
・Under Voltage Lock Out
・Short circuit protection with over voltage
・Mode-selectable the operating or stand-by mode by stand-by pin
・Synchronous operating the other BD9889FV IC’s
・BURST mode controlled by PWM and DC input
○Absolute Maximum Ratings（Ta = 25℃）
Parameter
Supply Voltage
Operating Temperature Range
Storage Temperature Range
Power Dissipation
Maximum Junction Temperature
*
Symbol
V
CC
Topr
Tstg
Pd
Tjmax
Limits
15
-40½+90
-55½+125
850
*
+125
Unit
V
℃
℃
mW
℃
Pd derate at 8.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm)
〇Recommended operating condition
Parameter
Supply voltage
CT oscillation frequency
BCT oscillation frequency
Symbol
V
CC
f
CT
f
BCT
Limits
5.0½14.0
20½150
0.05½0.50
Unit
V
kHz
kHz
Status of this document
The Japanese version of this document is the official specification.
Please use the translation version of this document as a reference to expedite understanding of the official version.
If these are any uncertainty in translation version of this document, official version takes priority.
REV. A
2/4
○Electric Characteristics（Ta=25℃，VCC=7V）
Parameter
（
（WHOLE DEVICE）
）
Operating current
Stand-by current
（
（OVER VOLTAGE DETECT）
）
FB overvoltage detect voltage
（
（STAND BY CONTROL）
）
Stand-by voltage H
Stand-by voltage L
Stand-by hysteresis
（
（TIMER LATCH）
）
Timer Latch voltage
Timer Latch current
（
（BURST MODE）
）
BOSC Max voltage
BOSC Min Voltage
BOSC constant current
BOSC frequency
（
（OSC BLOCK）
）
OSC constant current
OSC Max voltage
OSC Min voltage
MAX DUTY
Soft start current
IS COMP detect Voltage
SS COMP detect voltage
SRT ON resistance
（
（UVLO BLOCK）
）
Operating voltage
Shut down voltage
Operating voltage (External UVLO)
Lock out voltage (External UVLO)
Hysteresis width
（
（REG BLOCK）
）
REG output voltage
REG source current
VREF input voltage range
（
（FEED BACK BLOCK）
）
IS threshold voltage
VS threshold voltage
IS source current 1
IS source current 2
VS source current
（
（OUTPUT BLOCK）
）
NAch output voltage H
NBch output voltage H
NAch output voltage L
NBch output voltage L
NAch output sink resistance
NAch output source resistance
NBch output sink resistance
NBch output source resistance
Drive output frequency
（
（COMP BLOCK）
）
Over voltage detect
Under voltage detect
（
（PROTECT CLOCK）
）
Normal output voltage
Protect output voltage
V
P
H
V
P
L
2.9
－
3.1
－
3.3
0.5
V
V
Symbol
Icc1
Icc2
Vovf
VstH
VstL
⊿Vst
Vcp
Icp
VburH
VburL
I
BCT
F
BOSC
I
CT
VoscH
VoscL
MAXDUTY
Iss
Visc
Vss
R
SRT
VuvloH
VuvloL
Vuvlo1
Vuvlo2
⊿Vuvlo
V
REG
I
REG
VREF
Vis
Vvs
Iis1
Iis2
Ivs
VoutNAH
VoutNBH
VoutNAL
VoutNBL
RsinkNA
RsourceNA
RsinkNB
RsourceNB
f
OUT
V
COMP
H
V
COMP
L
MIN.
－
－
2.20
1.6
-0.3
0.08
1.9
0.5
1.94
0.4
1.35/BRT
266
1.35/RT
1.8
0.3
44
1.0
0.45
2.0
－
4.100
3.900
2.160
2.242
0.068
3.038
5.0
0.60
－
1.220
－
13.0
－
VCC-0.3
VCC-0.3
－
－
－
－
－
－
58.5
3.0
0.620
Limits
TYP.
11.0
2
2.40
－
－
0.18
2.0
1.0
2.0
0.5
1.5/BRT
280
1.5/RT
2.0
0.5
46.5
2.0
0.50
2.2
200
4.300
4.100
2.220
2.315
0.095
3.100
－
－
VREF
1.250
－
20.0
－
VCC-0.1
VCC-0.1
0.1
0.1
5
8
5
8
60.0
3.1
0.640
MAX.
17.0
10
2.60
V
CC
0.8
0.28
2.1
1.5
2.06
0.6
1.65/BRT
294
1.65/RT
2.2
0.7
49
3.0
0.55
2.4
400
4.500
4.300
2.280
2.388
0.122
3.162
－
1.50
－
1.280
1.5
27.0
1.0
－
－
0.3
0.3
10
16
10
16
61.5
3.2
0.660
Unit
mA
μA
V
V
V
V
V
μA
V
V
A
Hz
A
V
V
%
μA
V
V
Ω
V
V
V
V
V
V
mA
V
V
V
μA
μA
μA
V
V
V
V
Ω
Ω
Ω
Ω
KHz
V
V
DUTY=2.0V
DUTY=0V、IS=0.5V
VREF voltage
f
CT
=60kHz
f
CT
=60kHz
f
CT
=60kHz
f
BCT
=0.2kHz
f
BCT
=0.2kHz
BRT=33kΩ、BCT=0.050μF
System ＯＮ
System ＯＦＦ
Conditions
CT=0.5V
Isink = 10mA
Isource = 10mA
Isink = 10mA
Isource = 10mA
RT=18kΩ、CT=400pF
（This product is not designed to be radiation-resistant.）
REV. A
3/4
〇Package Dimensions
Device Mark
BD9889FV
１
SSOP-B28 (unit:mm)
〇Block Diagram
VCC
REG VREF
CT
RT
BRT BCT
DUTY
〇Pin Description
Pin No.
1
Pin
Name
DUTY
BRT
BCT
RT
SRT
CT
GND
FB1
IS1
VS1
FB2
IS2
VS2
VREF
FAIL
STB
COMP1
COMP2
UVLO
REG
SS
SCP
NA2
NB2
PGND
NB1
NA1
Vcc
Function
Control PWM mode and BURST mode
External resistor from BRT to GND for
adjusting the BURST triangle oscillator
External capacitor from BCT to GND for
adjusting the BURST triangle oscillator
External resistor from SRT to RT for
adjusting the triangle oscillator
External resistor from SRT to RT for
adjusting the triangle oscillator
External capacitor from CT to GND for
adjusting the triangle oscillator
GROUND
Error amplifier output①
Error amplifier input①
Error amplifier input②
Error amplifier output②
Error amplifier input③
Error amplifier input④
Reference voltage
Protect clock output
Stand-by switch
Over or under voltage detect for 1ch
Over or under voltage detect for 2ch
External Under Voltage Lock OUT
Internal regulator output
External capacitor from SS to GND for
Soft Start Control
External capacitor from SCP to GND for
Timer Latch
FET driver for 2ch
FET driver for 2ch
Ground for FET drivers
FET driver for 1ch
FET driver for 1ch
Supply voltage input
REG
BLOCK
OSC
BOSC
DUTY
BLOCK
2
3
STB
STB
BLOCK
SYSTEM ON/OFF
UVLO
BLOCK
VCC
UVLO
4
5
SS
FB1
IS1
VS1
F/B
BLOCK①
PWM
BLOCK①
LOGIC
BLOCK
①
VCC
OUTPUT
BLOCK①
NA1
NB1
SS
CT
6
7
FB2
IS2
VS2
F/B
BLOCK②
PWM
BLOCK②
LOGIC
BLOCK
②
VCC
OUTPUT
BLOCK②
NA2
NB2
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SS
CT
PGND
GND
PROTECT
BLOCK
FAIL
COMP1
COMP2
SCP
SRT
REV. A
4/4
〇
NOTE FOR USE
１. When designing the external circuit, including adequate margins for variation between external devices
and IC. Use adequate margins for steady state and transient characteristics.
２. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is
within recommended operating range. The standard electrical characteristic values cannot be guaranteed
at other voltages in the operating ranges, however the variation will be small.
３. Mounting failures, such as misdirection or miscounts, may harm the device.
４. A strong electromagnetic field may cause the IC to malfunction.
５. The GND pin should be the location within ±0.3V compared with the PGND pin.
６. BD9889FV incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD
circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to
protect the IC or guarantee its operation of the thermal shutdown circuit is assumed.
７. Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become
significantly shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical
countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings.
８. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage
is switching. Make sure to leave adequate margin for this IC variation.
９. On operating Slow Start Control (SS is less than 2.2V), It does not operate Timer Latch.
１０. By STB voltage, BD9889FV is changed to 2 states. Therefore, do not input STB pin voltage between one
state and the other state (0.8½1.6).
１１. The pin connected a connector need to connect to the resistor for electrical surge destruction.
This IC is a monolithic IC which (as shown is Fig-1) has P
+
substrate and between the various pins.
A P-N junction is formed from this P layer of each pin. For example, the relation between each potential
is as follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can
result in mutual interference among circuits as well as operation faults and physical damage. Accordingly
you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than
the GND (P substrate) voltage to an input pin.
１２．This IC is a monolithic IC which (as shown is Fig-1)has P
+
substrate and between the various pins. A
P-N junction is formed from this P layer of each pin. For example, the relation between each potential
is as follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can
result in mutual interference among circuits as well as operation faults and physical damage. Accordingly
you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than
the GND (P substrate) voltage to an input pin.
Resistance
(PinA)
(PinB)
C
Transistor (NPN)
B
E
GND
P
＋
P
N
P substrate
GND
Parasitic diode
N
P
＋
P substrate
GND
Parasitic diode
(PinB)
(PinA)
B
Parasitic diode
GND
Ｃ
Ｎ
Ｎ
N
N
Ｂ
C
Ｃ
E
Ｅ
GND
Other adjacent components
Parasitic diode
Fig-1 Simplified structure of a Bipolar IC
REV. A
Notice
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