Datasheet
Serial EEPROM Series Automotive EEPROM
125℃ Operation SPI BUS EEPROM
℃
BR25H128-2C
●
General Description
BR25H128-2C is a serial EEPROM of SPI BUS interface method.
●
Features
High speed clock action up to 10MHz (Max.)
Wait function by HOLDB terminal.
Part or whole of memory arrays settable as read only
memory area by program.
2.5V to 5.5V single power source action most
suitable
for battery use.
Page write mode useful for initial value write at
factory shipment.
For SPI bus interface (CPOL, CPHA)=(0, 0), (1, 1)
Self-timed programming cycle.
Low Supply Current
At write operation (5V)
: 1.2mA (Typ.)
At read operation (5V)
: 1.0mA (Typ.)
At standby operation (5V) : 0.1µA (Typ.)
Address auto increment function at read operation
Prevention of write mistake
Write prohibition at power on.
Write prohibition by command code (WRDI).
Write prohibition by WPB pin.
Write prohibition block setting by status registers
(BP1, BP0).
Prevention of write mistake at low voltage.
SOP8, SOP-J8 Package
Data at shipment Memory array: FFh, status register
WPEN, BP1, BP0 : 0
More than 100 years data retention.
More than 1 million write cycles.
AEC-Q100 Qualified.
●
Package
SOP8
5.00mm x 6.20mm x 1.71mm
SOP-J8
4.90mm x 6.00mm x 1.65mm
●
Page write
Number of pages
Product Number
64 Byte
BR25H128-2C
●
BR25H128-2C
Capacity
Bit Format
128Kbit
16Kx8
Product Number
BR25H128-2C
Supply Voltage
2.5V to 5.5V
SOP8
●
SOP-J8
●
○Product
structure：Silicon monolithic integrated circuit
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©2014 ROHM Co., Ltd. All rights reserved.
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○This
product is not designed protection against radioactive rays
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BR25H128-2C
●
Absolute maximum ratings (Ta=25°C)
Parameter
Supply Voltage
Symbol
VCC
Limits
-0.3 to +6.5
0.56(SOP8)
Permissible Dissipation
Pd
0.56(SOP-J8)
Storage Temperature Range
Operating Temperature Range
Terminal Voltage
Electrostatic Discharge Voltage
(Human Body Model)
Tstg
Topr
－
V
ESD
-65 to +150
-40 to +125
-0.3 to VCC+0.3
-6000 to +6000
*2
*1
Datasheet
Unit
V
W
°C
°C
V
V
・When
using at Ta=25℃ or higher, 4.5mW (*1,*2)to be reduced per 1℃
Caution:
Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over
the absolute maximum ratings.
●Memory
cell characteristics (VCC=2.5V to 5.5V)
Limits
Parameter
Min.
1,000,000
Write Cycles
*3
500,000
300,000
100
Data Retention
*3
60
50
*3: Not 100% TESTED
Unit
Typ.
－
－
－
－
－
－
Max.
－
－
－
－
－
－
Cycles
Cycles
Cycles
Years
Years
Years
Condition
Ta
≦
85°C
Ta
≦
105°C
Ta
≦
125°C
Ta
≦
25°C
Ta
≦
105°C
Ta
≦
125°C
●
Recommended Operating Ratings
Parameter
Supply Voltage
Input Voltage
Symbol
VCC
Vin
Limits
2.5
to
5.5
V
0 to VCC
Unit
●
Input / output capacity (Ta=25°C, frequency=5MHz)
Parameter
Input Capacity
*4
Output Capacity
*4
Symbol
C
IN
C
OUT
Conditions
V
IN
=GND
V
OUT
=GND
Min
－
－
Max
8
Unit
pF
8
*4: Not 100% TESTED
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BR25H128-2C
●
DC characteristics (Unless otherwise specified, Ta=-40°C to +125°C, VCC=2.5V to 5.5V)
Limits
Parameter
Symbol
Min.
Input High Voltage
Input Low Voltage
Output Low Voltage
Output High Voltage
Input Leakage
Current
Output Leakage
Current
VIH
VIL
VOL
VOH
ILI
ILO
0.7xVCC
-0.3
0
VCC-0.5
-2
-2
Typ.
－
－
－
－
－
－
Max.
VCC
+0.3
0.3x
VCC
0.4
VCC
+2
+2
V
V
V
V
2.5V≦VCC≦5.5V
2.5V≦VCC≦5.5V
IOL=2.1mA
IOH=-0.4mA
Unit Conditions
Datasheet
µA
V
IN
=0V to VCC
µA
V
OUT
=0V to VCC, CSB=VCC
VCC=2.5V,fSCK=5MHz, tE/W=4ms
mA VIH/VIL=0.9VCC/0.1VCC, SO=OPEN
Byte write, Page write, Write status register
VCC=5.5V,fSCK=5 or 10 MHz, tE/W=4ms
mA VIH/VIL=0.9VCC/0.1VCC, SO=OPEN
Byte write, Page write, Write status register
VCC=2.5V,fSCK=5MHz
mA VIH/VIL=0.9VCC/0.1VCC, SO=OPEN
Read, Read status register
VCC=5.5V,fSCK=5MHz
mA VIH/VIL=0.9VCC/0.1VCC, SO=OPEN
Read, Read status register
VCC=5.5V,fSCK=10MHz
mA VIH/VIL=0.9VCC/0.1VCC, SO=OPEN
Read, Read status register
VCC=5.5V
µA
CSB=HOLDB=WPB=VCC,
SCK=SI=VCC or =GND, SO=OPEN
ICC1
Supply Current
(WRITE)
ICC2
－
－
2.5
－
－
5.5
ICC3
Supply Current
(READ)
－
－
1.5
ICC4
－
－
2.0
ICC5
－
－
4.0
Standby Current
ISB
－
－
10
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TSZ02201-0R1R0G100130-1-2
8.Sep.2014 Rev.002
BR25H128-2C
●AC
characteristics (Ta=-40°C to +125°C, unless otherwise specified, load capacity C
L1
=100pF)
Parameter
SCK Frequency
SCK High Time
SCK Low Time
CSB High Time
CSB Setup Time
CSB Hold Time
SCK Setup Time
SCK Hold Time
SI Setup Time
SI Hold Time
Data Output Delay Time1
Data Output Delay Time2
(C
L2
=30pF)
Datasheet
Symbol
fSCK
tSCKWH
tSCKWL
tCS
tCSS
tCSH
tSCKS
tSCKH
tDIS
tDIH
tPD1
tPD2
tOH
tOZ
tHFS
tHFH
tHRS
tHRH
tHOZ
tHPD
tRC
tFC
*1
2.5V≦VCC≦5.5V
Min.
－
85
85
85
90
85
90
90
20
30
－
－
0
－
0
40
0
70
Typ.
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
Max.
5
－
－
－
－
－
－
－
－
－
60
50
－
100
－
4.5V≦VCC≦5.5V
Min.
－
40
40
40
30
30
30
30
10
10
－
－
0
－
0
30
0
30
Typ.
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
Max.
10
－
－
－
－
－
－
－
－
－
40
30
－
40
－
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ms
Output Hold Time
Output Disable Time
HOLDB Setting
Setup Time
HOLDB Setting
Hold Time
HOLDB Release
Setup Time
HOLDB Release
Hold Time
Time from HOLDB
to Output High-Z
Time from HOLDB
to Output Change
SCK Rise Time
*1
SCK Fall Time
*1
OUTPUT Rise Time
Write Time
*1 NOT 100% TESTED
－
－
－
－
－
－
－
－
－
－
－
－
－
－
100
70
1
1
40
40
4
－
－
40
40
1
1
40
40
4
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
tRO
tFO
tE/W
OUTPUT Fall Time
*1
●
AC measurement conditions
Parameter
Load Capacity 1
Load Capacity 2
Input Rise Time
Input Fall Time
Input Voltage
Input / Output
Judgment Voltage
Symbol
C
L1
C
L2
－
－
－
－
Limits
Min.
－
－
－
－
Typ.
－
－
－
－
Max.
100
30
50
50
Unit
Input Voltage
Input/Output judgement voltage
pF
pF
ns
ns
V
V
0.2Vcc
0.3Vcc
0.8Vcc
0.7Vcc
0.2VCC/0.8VCC
0.3VCC/0.7VCC
Figure 1. Input/Output judgment voltage
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TSZ02201-0R1R0G100130-1-2
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BR25H128-2C
●
Serial Input / Output Timing
tCS
tCSS
Datasheet
CSB
tSCKS
tSCKWL
tSCKWH
tRC
tFC
SCK
tDIS tDIH
SI
SO
High-Z
Figure 2. Input timing
SI is taken into IC inside in sync with data rise edge of SCK. Input address and data from the most significant bit MSB.
tCS
CSB
SCK
SI
tPD
tOH
tCSH tSCKH
tRO,tFO
tOZ
High-Z
SO
Figure 3. Input / Output timing
SO is output in sync with data fall edge of SCK. Data is output from the most significant bit MSB.
"H"
CSB
"L"
tHFS
tHFH
tHRS tHRH
SCK
tDIS
SI
n+1
tHOZ
n
tHPD
High-Z
Dn
n-1
SO
Dn+1
Dn
Dn-1
HOLDB
Figure 4. HOLD timing
●
Block diagram
CSB
SCK
VOLTAGE
INSTRUCTION DECODE
CONTROL CLOCK
GENERATION
WRITE
INHIBITION
DETECTION
HIGH VOLTAGE
GENERATOR
SI
HOLDB
INSTRUCTION
REGISTER
ADDRESS
REGISTER
14bit
STATUS REGISTER
ADDRESS
DECODER
14bit
128K
EEPROM
WPB
SO
DATA
REGISTER
8bit
READ/WRITE
AMP
8bit
Figure 5. Block diagram
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TSZ02201-0R1R0G100130-1-2
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