Am29BDS320G
Data Sheet
October 1, 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
27243
Revision
B
Amendment
1
Issue Date
October 1, 2003
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29BDS320G
32 Megabit (2 M x 16-Bit), 1.8 Volt-only
Simultaneous Read/Write, Burst Mode Flash Memory
Data Sheet
PRELIMINARY
Distinctive Characteristics
Architectural Advantages
Single 1.8 volt read, program and erase (1.65 to
1.95 volt)
Manufactured on 0.17 µm process technology
Enhanced VersatileIO™ (V
IO
) Feature
— Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the V
IO
pin
— 1.8V and 3V compatible I/O signals
Simultaneous Read/Write operation
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
— Four bank architecture: 8Mb/8Mb/8Mb/8Mb
Programmable Burst Interface
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with wrap-around
— Continuous Sequential Burst
Sector Architecture
— Eight 8 Kword sectors and sixty-two 32 Kword
sectors
— Banks A and D each contain four 8 Kword sectors and
fifteen 32 Kword sectors; Banks B and C each contain
sixteen 32 Kword sectors
— Eight 8 Kword boot sectors, four at the top of the
address range, and four at the bottom of the address
range
Minimum 1 million erase cycle guarantee per
sector
20-year data retention at 125°C
— Reliable operation for the life of the system
64-ball FBGA package
Hardware Features
Sector Protection
— Software command sector locking
Reduced Wait-State Handshaking feature available
— Provides host system with minimum possible latency
by monitoring RDY
Hardware reset input (RESET#)
— Hardware method to reset the device for reading
array data
WP# input
— Write protect (WP#) function protects sectors 0 and 1
(bottom boot), or sectors 68 and 69 (top boot),
regardless of sector protect status
ACC input: Acceleration function reduces
programming time; all sectors locked when ACC =
V
IL
CMOS compatible inputs, CMOS compatible outputs
Low V
CC
write inhibit
Software Features
Supports Common Flash Memory Interface (CFI)
Software command set compatible with JEDEC
42.4 standards
— Backwards compatible with Am29F and Am29LV
families
Data# Polling and toggle bits
— Provides a software method of detecting program
and erase operation completion
Erase Suspend/Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
Performance Charcteristics
Read access times at 54/40 MHz (at 30 pF)
— Burst access times of 13.5/20 ns
— Asynchronous random access times of 70 ns
— Initial Synchronous access times as fast as 87.5/95 ns
Power dissipation (typical values, C
L
= 30 pF)
— Burst Mode Read: 10 mA
— Simultaneous Operation: 25 mA
— Program/Erase: 15 mA
— Standby mode: 0.2 µA
Publication Number
27243
Revision
B
Amendment
1
Issue Date
October 1, 2003
P r e l i m i n a r y
General Description
The Am29BDS320G is a 32 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst
Mode Flash memory device, organized as 2,097,152 words of 16 bits each. This
device uses a single V
CC
of 1.65 to 1.95 V to read, program, and erase the mem-
ory array. The device supports Enhanced V
IO
to offer up to 3V compatible inputs
and outputs. A 12.0-volt V
ID
may be used for faster program performance if de-
sired. The device can also be programmed in standard EPROM programmers.
At 54 MHz, the device provides a burst access of 13.5 ns at 30 pF with a latency
of 87.5 ns at 30 pF. At 40 MHz, the device provides a burst access of 20 ns at 30
pF with a latency of 95 ns at 30 pF. The device operates within the industrial tem-
perature range of -40°C to +85°C. The device is offered in the 64-ball FBGA
package.
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory space into four banks. The device can improve overall
system performance by allowing a host system to program or erase in one bank,
then immediately and simultaneously read from another bank, with zero latency.
This releases the system from waiting for the completion of program or erase
operations.
The device is divided as shown in the following table:
Bank
A
B
C
D
Quantity
4
15
16
16
15
4
Size
8 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
8 Kwords
The Enhanced VersatileIO™ (V
IO
) control allows the host system to set the volt-
age levels that the device generates at its data outputs and the voltages tolerated
at its data inputs to the same voltage level that is asserted on the V
IO
pin. This
allows the device to operate in 1.8 V and 3 V system environments as required.
The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#)
and Output Enable (OE#) to control asynchronous read and write operations. For
burst operations, the device additionally requires Ready (RDY), and Clock (CLK).
This implementation allows easy interface with minimal glue logic to a wide range
of microprocessors/microcontrollers for high performance read operations.
The burst read mode feature gives system designers flexibility in the interface to
the device. The user can preset the burst length and wrap through the same
memory space, or read the flash array in continuous mode.
The clock polarity feature provides system designers a choice of active clock
edges, either rising or falling. The active clock edge initiates burst accesses and
determines when data will be output.
The device is entirely command set compatible with the
JEDEC 42.4 single-
power-supply Flash standard.
Commands are written to the command regis-
ter using standard microprocessor write timing. Register contents serve as inputs
to an internal state-machine that controls the erase and programming circuitry.
2
Am29BDS320G
27243B1 October 1, 2003
P r e l i m i n a r y
Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from
other Flash or EPROM devices.
The
Erase Suspend/Erase Resume
feature enables the user to put erase on
hold for any period of time to read data from, or program data to, any sector that
is not selected for erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation in progress and resets the
internal state machine to reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also reset the device, enabling
the system microprocessor to read boot-up firmware from the Flash memory
device.
The host system can detect whether a program or erase operation is complete by
using the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After
a program or erase cycle has been completed, the device automatically returns
to reading array data.
The
sector erase architecture
allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automat-
ically inhibits write operations during power transitions. The device also offers
two types of data protection at the sector level. The
sector lock/unlock com-
mand sequence
disables or re-enables both program and erase operations in
any sector. When at V
IL
,
WP#
locks sectors 0 and 1 (bottom boot device) or sec-
tors 68 and 69 (top boot device).
The device offers two power-saving features. When addresses have been stable
for a specified amount of time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consump-
tion is greatly reduced in both modes.
Spansion flash technology combines years of flash memory manufacturing expe-
rience to produce the highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector simultaneously via Fowler-
Nordheim tunnelling. The data is programmed using hot electron injection.
October 1, 2003 27243B1
Am29BDS320G
3
