Ultra Low Power CMOS SRAM
128K X 16 bit
Pb-Free and Green package materials are compliant to RoHS
BS616UV2019
n
FEATURES
Ÿ
Wide V
CC
low operation voltage :
C-grade : 1.8V ~ 3.6V
I-grade : 1.9V ~ 3.6V
Ÿ
Ultra low power consumption :
V
CC
= 2.0V
Operation current : 10mA (Max.) at 85ns
1mA (Max.) at 1MHz
Standby current : 0.2uA (Typ.) at 25
O
C
V
CC
= 3.0V
Operation current : 13mA (Max.) at 85ns
2mA (Max.) at 1MHz
Standby current : 0.3uA (Typ.) at 25
O
C
Ÿ
High speed access time :
-85
85ns (Max.)
-10
100ns (Max.)
Ÿ
Automatic power down when chip is deselected
Ÿ
Easy expansion with CE and OE options
Ÿ
I/O Configuration x8/x16 selectable by LB and UB pin.
Ÿ
Three state outputs and TTL compatible
Ÿ
Fully static operation
Ÿ
Data retention supply voltage as low as 1.5V
n
DESCRIPTION
The BS616UV2019 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 131,072 by 16 bits and
operates form a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.2uA at 2.0V/25
O
C and maximum access time of 85ns at
85
O
C.
Easy memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state output
drivers.
The BS616UV2019 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS616UV2019 is available in DICE form, JEDEC standard
48-pin TSOP Type I package and 48-ball BGA package.
n
POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
BS616UV2019DC
BS616UV2019AC
BS616UV2019TC
BS616UV2019AI
BS616UV2019TI
OPERATING
TEMPERATURE
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
V
CC
=2.0V
f
Max.
V
CC
=3.0V
V
CC
=2.0V
V
CC
=3.0V
1MHz
f
Max.
1MHz
Commercial
+0
O
C to +70
O
C
Industrial
-40
O
C to +85
O
C
DICE
3.0uA
2.0uA
1.5mA
11mA
0.8mA
8mA
BGA-48-0608
TSOP I-48
BGA-48-0608
TSOP I-48
5.0uA
3.0uA
2.0mA
13mA
1.0mA
10mA
n
PIN CONFIGURATIONS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
CE2
NC
UB
LB
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
A
B
C
D
E
F
G
H
LB
D8
D9
VSS
VCC
D14
D15
NC
2
OE
UB
D10
D11
D12
D13
NC
A8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
6
NC
D0
D2
VCC
VSS
D6
D7
NC
A16
NC
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
GND
CE
A0
n
BLOCK DIAGRAM
A6
A7
A8
A9
A10
A11
A15
A14
A13
A12
Address
Input
Buffer
10
Row
Decoder
1024
Memory Array
1024 x 2048
BS616UV2019TC
BS616UV2019TI
2048
DQ0
.
.
.
.
.
.
DQ15
16
.
.
.
.
.
.
Data
Input
Buffer
16
128
Column Decoder
7
Control
Address Input Buffer
16
Column I/O
Write Driver
Sense Amp
16
3
A0
A3
A5
NC
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE
D1
D3
D4
D5
WE
A11
Data
Output
Buffer
CE2,CE
WE
OE
UB
LB
V
CC
V
SS
A16 A0
A1
A2
A3
A4
A5
48-ball BGA top view
Brilliance Semiconductor, Inc.
reserves the right to change products and specifications without notice.
R0201-BS616UV2019
1
Revision 1.3
May.
2006
BS616UV2019
n
PIN DESCRIPTIONS
Name
A0-A16 Address Input
CE Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
Function
These 17 address inputs select one of the 262,144 x 16 bit in the RAM
CE is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected. (48B BGA ignore CE2 pin)
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
Lower byte and upper byte data input/output control pins.
OE Output Enable Input
LB and UB Data Byte Control Input
DQ0-DQ15 Data Input/Output
Ports
V
CC
V
SS
16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
n
TRUTH TABLE
MODE
Chip De-selected
(Power Down)
CE
H
X
X
L
CE2
(1)
X
L
X
H
H
WE
X
X
X
H
H
OE
X
X
X
H
H
LB
X
X
H
L
X
L
UB
X
X
H
X
L
L
L
H
L
L
H
DQ0~DQ7 DQ8~DQ15 V
CC
CURRENT
High Z
High Z
High Z
High Z
High Z
D
OUT
High Z
D
OUT
D
IN
X
D
IN
High Z
High Z
High Z
High Z
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
X
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
Output Disabled
L
Read
L
H
H
L
H
L
L
Write
L
H
L
X
H
L
1. 48BGA ignore CE2 condition.
2. H means V
IH
; L means V
IL
; X means don’t care (Must be V
IH
or V
IL
state)
R0201-BS616UV2019
2
Revision 1.3
May.
2006
BS616UV2019
n
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
(1)
n
OPERATING RANGE
UNITS
V
O
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
RATING
-0.5
(2)
to 5.0
-40 to +125
-60 to +150
1.0
20
RANG
Commercial
Industrial
AMBIENT
TEMPERATURE
0
O
C to + 70
O
C
-40
O
C to + 85
O
C
V
CC
1.8V ~ 3.6V
1.9V ~ 3.6V
C
C
O
W
mA
n
CAPACITANCE
(1)
(T
A
= 25 C, f = 1.0MHz)
O
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
C
IN
C
IO
Input
Capacitance
Input/Output
Capacitance
V
IN
= 0V
V
I/O
= 0V
6
8
pF
pF
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2.
–2.0V
in case of AC pulse width less than 30 ns.
1. This parameter is guaranteed and not 100% tested.
n
DC ELECTRICAL CHARACTERISTICS (T
A
= -40 C to +85 C)
PARAMETER
NAME
V
CC
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
(5)
I
CC1
I
CCSB
I
CCSB1
(6)
O
O
PARAMETER
Power Supply
TEST CONDITIONS
MIN.
1.9
V
CC
=2.0V
TYP.
(1)
--
MAX.
3.6
0.6
0.8
UNITS
V
Input Low Voltage
V
CC
=3.0V
V
CC
=2.0V
-0.3
(2)
1.4
2.2
--
--
V
Input High Voltage
V
CC
=3.0V
--
V
CC
+0.3
(3)
V
Input Leakage Current
V
IN
= 0V to V
CC
CE= V
IH
or CE2
(7)
= V
IL
V
I/O
= 0V to V
CC
,
CE= V
IH
or CE2
(7)
= V
IL
or OE = V
IH
V
CC
= Max, I
OL
= 0.1mA
V
CC
= Max, I
OL
= 2.0mA
V
CC
=2.0V
--
1
uA
Output Leakage Current
--
--
1
0.2
0.4
uA
Output Low Voltage
--
V
CC
=3.0V
V
CC
=2.0V
V
CC
=3.0V
V
CC
=2.0V
--
V
Output High Voltage
Operating Power Supply
Current
Operating Power Supply
Current
Standby Current
–
TTL
V
CC
= Min, I
OH
= -0.1mA
V
CC
= Min, I
OH
= -1.0mA
CE = V
IL
and CE2
(7)
= V
IH
,
I
IO
= 0mA, f = F
MAX(4)
CE = V
IL
and CE2
(7)
= V
IH
,
I
IO
= 0mA, f = 1MHz
CE = V
IH
or CE2
(7)
= V
IL
,
I
IO
= 0mA
CE≧V
CC
-0.2V or CE2
(7)
≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
1.6
2.4
--
--
--
10
13
V
--
mA
V
CC
=3.0V
V
CC
=2.0V
--
V
CC
=3.0V
V
CC
=2.0V
--
1.0
2.0
mA
--
V
CC
=3.0V
V
CC
=2.0V
--
0.2
0.3
0.5
1.0
mA
Standby Current
–
CMOS
--
V
CC
=3.0V
3.0
5.0
uA
1. Typical characteristics are at T
A
=25
O
C and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: V
CC
+1.0V in case of pulse width less than 20 ns.
4. F
MAX
=1/t
RC.
5. I
CC (MAX.)
is 8mA/11mA at V
CC
=2.0V/3.0V and T
A
=70
O
C.
6. I
CCSB1(MAX.)
is 2.0uA/3.0uA at V
CC
=2.0V/3.0V and T
A
=70
O
C.
7. 48B BGA ignore CE2 condition.
R0201-BS616UV2019
3
Revision 1.3
May.
2006
BS616UV2019
n
DATA RETENTION CHARACTERISTICS (T
A
= -40 C to +85 C)
SYMBOL
V
DR
(3)
I
CCDR
O
O
PARAMETER
V
CC
for Data Retention
TEST CONDITIONS
CE≧V
CC
-0.2V or CE2
(4)
≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
CE≧V
CC
-0.2V or CE2
(4)
≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
MIN.
1.5
TYP.
(1)
--
MAX.
--
UNITS
V
Data Retention Current
Chip Deselect to Data
Retention Time
--
0.1
1.0
uA
t
CDR
t
R
0
See Retention Waveform
t
RC (2)
--
--
ns
Operation Recovery Time
--
--
ns
1. V
CC
=1.5V, T
A
=25
O
C and not 100% tested.
2. t
RC
= Read Cycle Time.
3. I
CCDR(Max.)
is 0.7uA at T
A
=70
O
C.
4. 48B BGA ignore CE2 condition
n
LOW V
CC
DATA RETENTION WAVEFORM (1) (CE Controlled)
Data Retention Mode
V
CC
V
IH
V
CC
V
DR
≧1.5V
V
CC
t
CDR
CE≧V
CC
- 0.2V
t
R
V
IH
CE
n
LOW V
CC
DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
V
CC
V
DR
≧1.5V
V
CC
t
CDR
t
R
CE2≦0.2V
CE2
V
IL
V
IL
n
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
n
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM
“H”
TO
“L”
MAY CHANGE
FROM
“L”
TO
“H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE CHANGE
FROM
“H”
TO
“L”
WILL BE CHANGE
FROM
“L”
TO
“H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF”
STATE
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
Output Load
t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
Others
Vcc / 0V
1V/ns
0.5Vcc
C
L
= 5pF+1TTL
C
L
= 30pF+1TTL
ALL INPUT PULSES
1 TTL
Output
C
L(1)
V
CC
GND
10%
90%
90%
10%
→ ←
Rise Time:
1V/ns
→ ←
Fall Time:
1V/ns
1. Including jig and scope capacitance.
R0201-BS616UV2019
4
Revision 1.3
May.
2006
BS616UV2019
n
AC ELECTRICAL CHARACTERISTICS (T
A
= -40 C to +85 C)
READ CYCLE
JEDEC
PARANETER
PARAMETER
NAME
NAME
CYCLE TIME : 85ns CYCLE TIME : 100ns
(V
CC
=1.9~3.6V)
(V
CC
=1.9~3.6V)
MIN. TYP. MAX. MIN. TYP. MAX.
85
--
(CE)
(CE2)
(LB, UB)
--
--
--
--
(CE)
(CE2)
(LB, UB)
15
15
15
15
(CE)
(CE2)
--
--
--
--
15
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
85
85
85
85
40
--
--
--
--
35
35
35
30
--
100
--
--
--
--
--
15
15
15
15
--
--
--
--
15
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
100
100
50
--
--
--
--
40
40
40
35
--
O
O
DESCRIPTION
UNITS
t
AVAX
t
AVQX
t
ELQV1
t
ELQV2
t
BLQV
t
GLQV
t
ELQX1
t
ELQX2
t
BLQX
t
GLQX
t
EHQZ1
t
EHQZ2
t
BHQZ
t
GHQZ
t
AVQX
t
RC
t
AA
t
ACS1
t
ACS2
t
BA
t
OE
t
CLZ1
t
CLZ2
t
BE
t
OLZ
t
CHZ1
t
CHZ2
t
BDO
t
OHZ
t
OH
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output Low Z
Chip Select to Output High Z
Chip Select to Output High Z
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Byte Control to Output High Z (LB, UB)
Output Enable to Output High Z
Data Hold from Address Change
n
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1
(1,2,4)
t
RC
ADDRESS
t
OH
D
OUT
t
AA
t
OH
R0201-BS616UV2019
5
Revision 1.3
May.
2006
