BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
256K X 8 bit
DESCRIPTION
BS62LV2008
• Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade: 53mA (@55ns) operating current
I -grade: 55mA (@55ns) operating current
C-grade: 43mA (@70ns) operating current
I -grade: 45mA (@70ns) operating current
1.0uA(Typ.) CMOS standby current
• High speed access time :
-55
55ns
-70
70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
The BS62LV2008 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates from a range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
1.0u
A
at 5.0
V
/25
o
C
and maximum access time of 55ns at 5.0
V
/ 85
o
C
.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV2008 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2008 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 8mmx13.4mm STSOP and 8mmx20mm TSOP.
PRODUCT FAMILY
PRODUCT
FAMILY
BS62LV2008DC
BS62LV2008TC
BS62LV2008STC
BS62LV2008SC
BS62LV2008DI
BS62LV2008TI
BS62LV2008STI
BS62LV2016SI
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
( ns )
55ns: 4.5~5.5V
70ns: 4.5~5.5V
( I
CCSB1
, Max )
Vcc=5.0V
POWER DISSIPATION
STANDBY
Operating
( I
CC
, Max )
Vcc=5.0V
55ns
70ns
PKG TYPE
DICE
TSOP-32
STSOP-32
SOP-32
DICE
TSOP-32
STSOP-32
SOP-32
+0 C to +70 C
O
O
4.5V ~5.5V
55/70
10uA
53mA
43mA
-40
O
C to +85
O
C
4.5V ~ 5.5V
55/70
30uA
55mA
45mA
PIN CONFIGURATIONS
BLOCK DIAGRAM
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
A13
A17
A15
A16
A14
A12
A7
A6
A5
A4
•
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BS62LV2008TC
BS62LV2008STC
BS62LV2008TI
BS62LV2008STI
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
BS62LV2008SC
8
BS62LV2008SI
9
10
11
12
13
14
15
16
A11
A9
A8
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
Address
Input
Buffer
20
Row
Decoder
1024
Memory Array
1024 x 2048
2048
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
256
Column Decoder
16
Control
Address Input Buffer
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
Brilliance Semiconductor, Inc
.
reserves the right to modify document contents without notice.
R0201-BS62LV2008
•
8
Data
Output
Buffer
8
CE1
CE2
WE
OE
Vdd
Gnd
A11 A9 A8 A3 A2 A1 A0 A10
1
Revision 1.1
Jan.
2004
BSI
PIN DESCRIPTIONS
BS62LV2008
Function
These 18 address inputs select one of the 262,144 x 8-bit words in the RAM
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
Name
A0-A17 Address Input
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0-DQ7 Data Input/Output
Ports
Vcc
Gnd
These 8 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
TRUTH TABLE
MODE
WE
CE1
CE2
OE
I/O OPERATION
Vcc CURRENT
Not selected
(Power Down)
Output Disabled
Read
Write
X
X
H
H
L
H
X
L
L
L
X
L
H
H
H
X
X
H
L
X
High Z
High Z
D
OUT
D
IN
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
OPERATING RANGE
UNITS
V
O
RATING
-0.5 to
Vcc+0.5
-40 to +85
-60 to +150
1.0
20
RANGE
Commercial
Industrial
AMBIENT
TEMPERATURE
0 C to +70 C
-40 C to +85 C
O
O
O
O
Vcc
4.5V ~ 5.5V
4.5V ~ 5.5V
C
C
O
W
mA
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
C
IN
C
DQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
V
IN
=0V
V
I/O
=0V
6
8
pF
pF
1. This parameter is guaranteed and not 100% tested.
R0201-BS62LV2008
2
Revision 1.1
Jan.
2004
BSI
DC ELECTRICAL CHARACTERISTICS
( TA = -40
o
C to + 85
o
C )
PARAMETER
NAME
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
(5)
BS62LV2008
TEST CONDITIONS
Vcc=5.0V
Vcc=5.0V
PARAMETER
Guaranteed Input Low
(3)
Voltage
Guaranteed Input High
(3)
Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Standby Current-TTL
MIN.
-0.5
2.2
--
--
Vcc=5.0V
Vcc=5.0V
TYP.
(1)
MAX.
--
--
--
--
--
--
--
--
0.8
V
cc
+0.3
1
1
0.4
--
45
55
1.0
UNITS
V
V
uA
uA
V
V
mA
mA
Vcc = Max, V
IN
= 0V to Vcc
Vcc = Max, CE1= V
IH
, CE2= V
IL,
or
OE = V
IH
, V
I/O
= 0V to Vcc
Vcc = Max, I
OL
= 2.0mA
Vcc = Min, I
OH
= -1.0mA
CE1 = V
IL
, CE2 = V
IH
,
(2)
I
DQ
= 0mA, F = Fmax
CE1 = V
IH
, or CE2 = V
IL
,
I
DQ
= 0mA,
CE1≧Vcc-0.2V or CE2≦0.2V,
V
IN
≧Vcc-0.2V
or V
IN
≦0.2V
--
2.4
--
--
5.0 V
70ns
55ns
I
CCSB
(4)
Vcc=5.0V
I
CCSB1
Standby Current-CMOS
Vcc=5.0V
--
1.0
30
uA
1. Typical characteristics are at T
A
= 25
o
C.
2. Fmax = 1/t
RC
.
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. I
cc
s
B1
_Max.
is 10uA at Vcc=5.0V and T
A
=70
o
C.
5. Icc
_Max.
is 53mA(@55ns) / 43mA(@70ns) at Vcc=5.0V and T
A
=0~70
o
C.
DATA RETENTION CHARACTERISTICS
( TA = -40
o
C to + 85
o
C )
SYMBOL
V
DR
I
CCDR
(3)
t
CDR
t
R
PARAMETER
Vcc for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
TEST CONDITIONS
CE1
≧
Vcc - 0.2V or CE2
≦
0.2V,
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
CE1
≧
Vcc - 0.2V or CE2
≦
0.2V,
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
See Retention Waveform
MIN.
1.5
--
0
T
RC (2)
TYP.
(1)
--
0.1
--
--
MAX.
--
1.0
--
--
UNITS
V
uA
ns
ns
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
3. Icc
DR_MAX.
is 0.7uA at T
A
=70
o
C.
LOW V
CC
DATA RETENTION WAVEFORM (1)
( CE1 Controlled )
Data Retention Mode
V
DR
≥
1.5V
Vcc
V
IH
Vcc
Vcc
t
CDR
CE1
≥
Vcc - 0.2V
t
R
V
IH
CE1
LOW V
CC
DATA RETENTION WAVEFORM (2)
( CE2 Controlled )
Data Retention Mode
Vcc
Vcc
V
DR
≧
1.5V
Vcc
t
CDR
t
R
CE2
≦
0.2V
CE2
R0201-BS62LV2008
V
IL
V
IL
3
Revision 1.1
Jan.
2004
BSI
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
BS62LV2008
KEY TO SWITCHING WAVEFORMS
Vcc / 0V
1V/ns
0.5Vcc
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
C
L
= 100pF+1TTL
C
L
= 30pF+1TTL
,
AC ELECTRICAL CHARACTERISTICS
( TA = -40
o
C to + 85
o
C)
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Data Hold from Address Change
CYCLE TIME : 55ns
(Vcc = 4.5~5.5V)
CYCLE TIME : 70ns
(Vcc = 4.5~5.5V)
MIN. TYP. MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN. TYP. MAX.
t
AVAX
t
AVQV
t
E1LQV
t
E2HOV
t
GLQV
t
E1LQX
t
E2HOX
t
GLQX
t
E1HQZ
t
E2HQZ
t
GHQZ
t
AXOX
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
CLZ1
t
CLZ2
t
OLZ
t
CHZ1
t
CHZ2
t
OHZ
t
OH
55
--
(CE1)
(CE2)
(CE1)
(CE2)
(CE1)
(CE2)
--
--
--
10
10
5
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
55
30
--
--
--
30
30
25
--
70
--
--
--
--
10
10
5
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
70
35
--
--
--
35
35
30
--
R0201-BS62LV2008
4
Revision 1.1
Jan.
2004
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
BS62LV2008
t
RC
ADDRESS
t
D
OUT
t
OH
AA
t
OH
READ CYCLE2
CE1
(1,3,4)
t
CE2
(5)
CLZ
ACS1
t
t
ACS2
t
CHZ1,
t
(5)
CHZ2
D
OUT
(1,4)
READ CYCLE3
t
RC
ADDRESS
t
OE
AA
t
CE1
OE
t
OH
t
t
(5)
CLZ1
OLZ
t
ACS1
t
OHZ
(5)
(1,5)
t
CHZ1
CE2
t
t
(5)
CLZ2
ACS2
t
(2,5)
CHZ2
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
IL
and CE2= V
IH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = V
IL
.
5. The parameter is guaranteed but not 100% tested.
R0201-BS62LV2008
5
Revision 1.1
Jan.
2004
嵌入式系统
