BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
32K X 8 bit
DESCRIPTION
BS62LV2563
• Wide Vcc operation voltage : 2.4V ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.01uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
The BS62LV2563 is a high performance , very low power CMOS
Static Random Access Memory organized as 32,768 words by 8 bits
and operates from a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.01uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip enable(CE)
,and active LOW output enable(OE) and three-state output drivers.
The BS62LV2563 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2563 is available in the JEDEC standard 28 pin 330mil
Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP and 8mmx13.4mm
TSOP (normal type).
PRODUCT FAMILY
PRODUCT
FAMILY
BS62LV2563SC
BS62LV2563TC
BS62LV2563PC
BS62LV2563JC
BS62LV2563DC
BS62LV2563SI
BS62LV2563TI
BS62LV2563PI
BS62LV2563JI
BS62LV2563DI
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
(ns)
Vcc=3.0V
POWER DISSIPATION
STANDBY
Operating
(I
CCSB1
, Max)
Vcc=3.0V
(I
CC
, Max)
Vcc=3.0V
PKG
TYPE
SOP-28
TSOP-28
PDIP-28
SOJ-28
DICE
SOP-28
TSOP-28
PDIP-28
SOJ-28
DICE
0 C to +70 C
O
O
2.4V ~ 3.6V
70
0.2uA
20mA
-40 C to +85 C
O
O
2.4V ~ 3.6V
70
0.4uA
25mA
PIN CONFIGURATIONS
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
28
27
26
25
BLOCK DIAGRAM
VCC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
A5
A6
A7
A12
A14
A13
A8
A9
A11
Buffer
5
BS62LV2563SC
24
6
BS62LV2563SI
23
7
BS62LV2563PI
8
9
10
11
12
13
14
BS62LV2563PC
BS62LV2563JC
BS62LV2563JI
•
Address
Input
18
Row
Decoder
512
Memory Array
512 x 512
22
21
20
19
18
17
16
15
512
Column I/O
Write Driver
Sense Amp
64
Column Decoder
12
CE
WE
OE
Vdd
Gnd
A4 A3 A2 A1 A0 A10
Control
Address Input Buffer
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
BS62LV2563TC
BS62LV2563TI
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
8
Data
Output
Buffer
8
Brilliance Semiconductor, Inc
.
reserves the right to modify document contents without notice.
R0201-BS62LV2563
•
1
Revision 2.3
Jan.
2004
BSI
PIN DESCRIPTIONS
BS62LV2563
Function
These 15 address inputs select one of the 32768 x 8-bit words in the RAM
CE is active LOW. Chip enables must be active when data read from or write to the
device. If chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
Name
A0-A14 Address Input
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
DQ0-DQ7 Data Input/Output
Ports
Vcc
Gnd
TRUTH TABLE
MODE
Not selected
Output Disabled
Read
Write
WE
X
H
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O OPERATION
High Z
High Z
D
OUT
D
IN
Vcc CURRENT
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
PARAMETER
Terminal Voltage
Respect to GND
with
OPERATING RANGE
UNITS
V
O
RATING
-0.5 to
Vcc+0.5
-40 to +125
-60 to +150
1.0
20
RANGE
Commercial
Industrial
AMBIENT
TEMPERATURE
0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
2.4V ~ 3.6V
2.4V ~ 3.6V
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
C
C
O
W
mA
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
SYMBOL
C
IN
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
V
IN
=0V
MAX.
UNIT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
6
8
pF
pF
C
DQ
V
I/O
=0V
1. This parameter is guaranteed and not 100% tested.
R0201-BS62LV2563
2
Revision 2.3
Jan.
2004
BSI
DC ELECTRICAL CHARACTERISTICS
( TA = 0
o
C to + 70
o
C)
PARAMETER
NAME
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
BS62LV2563
TEST CONDITIONS
Vcc=3.0V
Vcc=3.0V
PARAMETER
Guaranteed Input Low
(2)
Voltage
Guaranteed Input High
(2)
Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Standby Current-TTL
MIN.
-0.5
2.0
--
--
Vcc=3.0V
Vcc=3.0V
TYP.
(1)
MAX.
--
--
--
--
--
--
--
0.8
Vcc
+0.2
1
1
0.4
--
20
UNITS
V
V
uA
uA
V
V
mA
Vcc = Max, V
IN
= 0V to Vcc
Vcc = Max, CE = V
IH
, or OE = V
IH
,
V
I/O
= 0V to Vcc
Vcc = Max, I
OL
= 2mA
Vcc = Min, I
OH
= -1mA
CE = V
IL
, I
DQ
= 0mA, F = Fmax
(3)
--
2.4
--
Vcc=3.0V
I
CCSB
CE = V
IH
, I
DQ
= 0mA
CE
≧
Vcc-0.2V,
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
Vcc=3.0V
--
--
1
mA
I
CCSB1
Standby Current-CMOS
Vcc=3.0V
--
0.01
0.2
uA
1. Typical characteristics are at TA = 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
RC
.
DATA RETENTION CHARACTERISTICS
( TA = 0
o
C to + 70
o
C)
SYMBOL
V
DR
I
CCDR
t
CDR
t
R
PARAMETER
Vcc for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
TEST CONDITIONS
CE
≧
Vcc - 0.2V
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
CE
≧
Vcc -0.2V
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
See Retention Waveform
MIN.
1.5
--
0
T
RC (2)
TYP.
(1)
--
0.01
--
--
MAX.
--
0.20
--
--
UNITS
V
uA
ns
ns
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
LOW V
CC
DATA RETENTION WAVEFORM (1)
( CE Controlled )
Data Retention Mode
Vcc
V
IH
Vcc
V
DR
≥
1.5V
Vcc
t
CDR
CE
≥
Vcc - 0.2V
t
R
V
IH
CE
R0201-BS62LV2563
3
Revision 2.3
Jan.
2004
BSI
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
1V/ns
0.5Vcc
WAVEFORM
BS62LV2563
KEY TO SWITCHING WAVEFORMS
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC TEST LOADS AND WAVEFORMS
3.3V
OUTPUT
100PF
INCLUDING
JIG AND
SCOPE
1269
Ω
3.3V
OUTPUT
1269
Ω
,
5PF
1404
Ω
INCLUDING
JIG AND
SCOPE
1404
Ω
FIGURE 1A
THEVENIN EQUIVALENT
667
Ω
FIGURE 1B
OUTPUT
1.73V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
←
→
←
5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS
( TA = 0
o
C to + 70
o
C,Vcc=3.0V)
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Output Disable to Output Address Change
CYCLE TIME : 70ns
MIN. TYP. MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AVAX
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXOX
t
RC
t
AA
t
ACS
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
70
--
--
--
10
10
0
0
10
--
--
--
--
--
--
--
--
--
--
70
70
50
--
--
35
30
--
R0201-BS62LV256
R0201-BS62LV2563
4
Revision 2.3
Jan.
2004
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
BS62LV2563
t
RC
ADDRESS
t
D
OUT
t
OH
AA
t
OH
READ CYCLE2
(1,3,4)
CE
t
t
D
OUT
(5)
CLZ
ACS
t
CHZ
(5)
READ CYCLE3
(1,4)
t
RC
ADDRESS
t
OE
AA
t
OE
CE
t
OH
t
OLZ
t
ACS
t
CLZ
(5)
t
OHZ
(5)
(1,5)
t
CHZ
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V
IL
.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. Transition is measured
±
500mV from steady state with C
L
= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
R0201-BS62LV2563
5
Revision 2.3
Jan.
2004
