Very Low Power CMOS SRAM
512K X 8 bit
Pb-Free and Green package materials are compliant to RoHS
BS62LV4006
n
FEATURES
Ÿ
Wide V
CC
operation voltage : 2.4V ~ 5.5V
Ÿ
Very low power consumption :
V
CC
= 3.0V
Operation current : 30mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 0.25uA (Typ.) at 25
O
C
V
CC
= 5.0V
Operation current : 70mA (Max.) at 55ns
10mA (Max.) at 1MHz
Standby current : 1.5uA (Typ.) at 25
O
C
Ÿ
High speed access time :
-55
55ns (Max.) at V
CC
=3.0~5.5V
-70
70ns (Max.) at V
CC
=2.7~5.5V
Ÿ
Automatic power down when chip is deselected
Ÿ
Easy expansion with CE and OE options
Ÿ
Three state outputs and TTL compatible
Ÿ
Fully static operation
Ÿ
Data retention supply voltage as low as 1.5V
n
DESCRIPTION
The BS62LV4006 is a high performance, very low power CMOS
Static Random Access Memory organized as 524,288 by 8 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.25uA at 3.0V/25
O
C and maximum access time of 55ns at
3.0V/85
O
C.
Easy memory expansion is provided by an active LOW chip enable
(CE), and active LOW output enable (OE) and three-state output
drivers.
The BS62LV4006 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS62LV4006 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 600mil Plastic DIP, 400 mil TSOP II,
8mmx13.4mm STSOP and 8mmx20mm TSOP package.
n
POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
BS62LV4006DC
BS62LV4006EC
BS62LV4006HC
BS62LV4006PC
BS62LV4006SC
BS62LV4006STC
BS62LV4006TC
BS62LV4006EI
BS62LV4006HI
BS62LV4006PI
BS62LV4006SI
BS62LV4006STI
BS62LV4006TI
OPERATING
TEMPERATURE
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
V
CC
=3V
10MHz
f
Max.
V
CC
=5.0V
V
CC
=3.0V
1MHz
V
CC
=5V
10MHz
f
Max.
1MHz
Commercial
+0
O
C to +70
O
C
10uA
2.0uA
9mA
43mA
68mA
1.5mA
18mA
29mA
Industrial
-40
O
C to +85
O
C
20uA
4.0uA
10mA
45mA
70mA
2mA
20mA
30mA
DICE
TSOP II-32
BGA-36-0608
PDIP-32
SOP-32
STSOP-32
TSOP-32
TSOP II-32
BGA-36-0608
PDIP-32
SOP-32
STSOP-32
TSOP-32
n
PIN CONFIGURATIONS
n
BLOCK DIAGRAM
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
A12
A14
A16
A18
A15
A17
A13
A8
A9
A11
•
BS62LV4006TC
BS62LV4006TI
BS62LV4006STC
BS62LV4006STI
1
2
A1
A11
A9
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Address
Input
Buffer
10
Row
Decoder
1024
Memory Array
1024 x 4096
4096
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
256
Column Decoder
9
8
Column I/O
Write Driver
Sense Amp
3
NC
4
A3
5
A6
6
A8
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
•
BS62LV4006EC
BS62LV4006EI
BS62LV4006SC
BS62LV4006SI
BS62LV4006PC
BS62LV4006PI
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
A
A0
8
B
DQ4
A2
WE
A4
A7
DQ0
Data
Output
Buffer
C
DQ5
NC
A5
DQ1
D
VSS
VCC
CE
WE
Control
Address Input Buffer
E
VCC
VSS
OE
V
CC
GND
A7 A6 A5 A4 A3 A2 A1 A0 A0
F
DQ6
A18
A17
DQ2
G
DQ7
OE
CE
A16
A15
DQ3
H
A9
A10
A11
A12
A13
A14
36-ball BGA top view
Brilliance Semiconductor, Inc.
reserves the right to change products and specifications without notice.
R0201-BS62LV4006
1
Revision 1.4
May.
2006
BS62LV4006
n
PIN DESCRIPTIONS
Name
A0-A18 Address Input
CE Chip Enable Input
Function
These 19 address inputs select one of the 524,288 x 8-bit in the RAM
CE is active LOW. Chip enable must be active when data read form or write to the
device. If chip enable is not active, the device is deselected and is in standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
There 8 bi-directional ports are used to read data from or write data into the RAM.
WE Write Enable Input
OE Output Enable Input
DQ0-DQ7 Data Input/Output
Ports
V
CC
GND
Power Supply
Ground
n
TRUTH TABLE
MODE
Not selected
(Power Down)
Output Disabled
Read
Write
CE
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
I/O OPERATION
High Z
High Z
D
OUT
D
IN
V
CC
CURRENT
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
n
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
(1)
n
OPERATING RANGE
UNITS
V
O
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
RATING
-0.5
(2)
to 7.0
-40 to +125
-60 to +150
1.0
20
RANG
Commercial
Industrial
AMBIENT
TEMPERATURE
0
O
C to + 70
O
C
-40
O
C to + 85
O
C
V
CC
2.4V ~ 5.5V
2.4V ~ 5.5V
C
C
O
W
mA
n
CAPACITANCE
(1)
(T
A
= 25 C, f = 1.0MHz)
O
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
C
IN
C
IO
Input
Capacitance
Input/Output
Capacitance
V
IN
= 0V
V
I/O
= 0V
6
8
pF
pF
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2.
–2.0V
in case of AC pulse width less than 30 ns.
R0201-BS62LV4006
1. This parameter is guaranteed and not 100% tested.
2
Revision 1.4
May.
2006
BS62LV4006
n
DC ELECTRICAL CHARACTERISTICS (T
A
= -40 C to +85 C)
PARAMETER
NAME
V
CC
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
(5)
I
CC1
I
CCSB
I
CCSB1
(6)
PARAMETER
Power Supply
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Operating Power Supply
Current
Standby Current
–
TTL
Standby Current
–
CMOS
V
CC
= Max, V
IN
= 0V to V
CC
V
CC
= Max, CE= V
IH
, or OE = V
IH
,
V
I/O
= 0V to V
CC
V
CC
= Max, I
OL
= 2.0mA
V
CC
= Min, I
OH
= -1.0mA
CE = V
IL
,
I
DQ
= 0mA, f = F
MAX(4)
CE = V
IL
,
I
DQ
= 0mA, f = 1MHz
CE = V
IH
,
I
DQ
= 0mA
CE≧V
CC
-0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
V
CC
=3.0V
V
CC
=5.0V
V
CC
=3.0V
V
CC
=5.0V
V
CC
=3.0V
V
CC
=5.0V
V
CC
=3.0V
V
CC
=5.0V
O
O
TEST CONDITIONS
MIN.
2.4
-0.5
(2)
2.2
--
--
--
2.4
--
--
--
--
TYP.
(1)
--
--
--
--
--
--
--
--
--
--
0.25
1.5
MAX.
5.5
0.8
V
CC
+0.3
(3)
1
1
0.4
--
30
70
2
10
0.5
1.0
4.0
20
UNITS
V
V
V
UA
UA
V
V
mA
mA
mA
uA
1. Typical characteristics are at T
A
=25
O
C and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: V
CC
+1.0V in case of pulse width less than 20 ns.
4. F
MAX
=1/t
RC.
5. I
CC (MAX.)
is 29mA/68mA at V
CC
=3.0V/5.0V and T
A
=70
O
C.
6. I
CCSB1(MAX.)
is 2.0uA/10uA at V
CC
=3.0V/5.0V and T
A
=70
O
C.
n
DATA RETENTION CHARACTERISTICS (T
A
= -40 C to +85 C)
SYMBOL
V
DR
I
CCDR
(3)
t
CDR
t
R
PARAMETER
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
O
O
TEST CONDITIONS
CE≧V
CC
-0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
CE≧V
CC
-0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
MIN.
1.5
--
0
TYP.
(1)
--
0.1
--
--
MAX.
--
1.5
--
--
UNITS
V
uA
ns
ns
See Retention Waveform
t
RC (2)
1. V
CC
=1.5V, T
A
=25
O
C and not 100% tested.
2. t
RC
= Read Cycle Time.
3. I
CCRD(Max.)
is 1.0uA at T
A
=70
O
C.
n
LOW V
CC
DATA RETENTION WAVEFORM (1) (CE Controlled)
Data Retention Mode
V
CC
V
IH
V
CC
V
DR
≧1.5V
V
CC
t
CDR
CE≧V
CC
- 0.2V
t
R
V
IH
CE
R0201-BS62LV4006
3
Revision 1.4
May.
2006
BS62LV4006
n
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM
“H”
TO
“L”
MAY CHANGE
FROM
“L”
TO
“H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE CHANGE
FROM
“H”
TO
“L”
WILL BE CHANGE
FROM
“L”
TO
“H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF”
STATE
n
KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
Output Load
t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
Others
Vcc / 0V
1V/ns
0.5Vcc
C
L
= 5pF+1TTL
C
L
= 30pF+1TTL
ALL INPUT PULSES
1 TTL
Output
C
L(1)
V
CC
GND
10%
90%
90%
10%
→ ←
Rise Time :
1V/ns
→ ←
Fall Time :
1V/ns
1. Including jig and scope capacitance.
n
AC ELECTRICAL CHARACTERISTICS (T
A
= -40 C to +85 C)
READ CYCLE
JEDEC
PARANETER
PARAMETER
NAME
NAME
CYCLE TIME : 55ns
(V
CC
= 3.0~5.5V)
MIN. TYP. MAX.
55
--
--
--
10
5
--
--
10
--
--
--
--
--
--
--
--
--
--
55
55
30
--
--
30
25
--
CYCLE TIME : 70ns
(V
CC
= 2.7~5.5V)
MIN. TYP. MAX.
70
--
--
--
10
5
--
--
10
--
--
--
--
--
--
--
--
--
--
70
70
35
--
--
35
30
--
O
O
DESCRIPTION
UNITS
t
AVAX
t
AVQX
t
E1LQV
t
GLQV
t
E1LQX
t
GLQX
t
E1HQZ
t
GHQZ
t
AVQX
t
RC
t
AA
t
ACS
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output Low Z
Chip Select to Output High Z
Output Enable to Output High Z
Data Hold from Address Change
ns
ns
ns
ns
ns
ns
ns
ns
ns
R0201-BS62LV4006
4
Revision 1.4
May.
2006
BS62LV4006
n
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1
(1,2,4)
t
RC
ADDRESS
t
OH
D
OUT
t
AA
t
OH
READ CYCLE 2
(1,3,4)
CE
t
ACS
t
CLZ
D
OUT
(5)
t
CHZ
(5)
READ CYCLE 3
(1, 4)
t
RC
ADDRESS
t
AA
OE
t
OE
CE
(5)
t
OH
t
OLZ
t
ACS
t
CLZ
t
OHZ
t
CHZ
(5)
(1,5)
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V
IL
.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. Transition is measured
±
500mV from steady state with C
L
= 5pF.
The parameter is guaranteed but not 100% tested.
R0201-BS62LV4006
5
Revision 1.4
May.
2006
