BU-65570V, BU-65572V
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Card you purchase
has...
®
MIL-STD-1553B, BC/RT/MT VME/VXI
QUAD TESTER/SIMULATOR CARD
FEATURES
•
VME/VXI Format, One to Four 1553
Buses
•
Variable Amplitude Transceivers
•
64K Words of Shared RAM per Bus
•
Simultaneous Emulation of BC, 31
RT’s, and MT for Each Bus
•
IRIG-B Interface
•
DMA Data Transfers via VME Master
Operation
•
Software Configuration of Bus
Coupling and Termination
•
VXI Plug and Play Compatible
DESCRIPTION
DDC's BU-65570V/72V is a versatile, VME/VXI Card designed for the
test and simulation of MIL-STD-1553 systems. It provides full, intelli-
gent interfacing for one to four serial dual redundant MIL-STD-1553
data buses and a VME/VXI chassis. The BU-65570V is a fixed volt-
age output 1553 card, and the BU-65572V is a variable voltage out-
put 1553 card.
The BU-65572V is designed with a variable voltage output transceiv-
er for each of the four buses. The output of these transceivers is con-
trolled by software with a minimum of 0 V and a maximum of 21.5 V
over 1024 steps.
One of the new features designed into the BU-65570V/72V is VME
Master Mode. The master mode provides the capability to transfer
blocks of data to the host via Direct Memory Access.
The BU-65570V/72V cards provide software controllable bus con-
nection and configuration (transformer or direct) as well as software
configuration for bus termination. The bus termination is programma-
ble to one of three values: None, Full (37.5 ohms), and Half
(75.0 ohms).
'C' programming libraries are supplied with the card. These libraries
provide complete control of the board’s capabilities. Software control
of bus loading, bus coupling and IRIG configuration is provided by the
library functions developed for this card.
The software libraries also provide access to the playback capabili-
ties of the board. Each of the four buses is able to simultaneously
replay and monitor previously recorded bus activity in real time.
•
32-Bit Time Tag with 1µsec resolution
•
Support for VxWorks® (Power PC)
and Windows NT®
•
Replay of previously recorded Bus
Traffic via Menu and Runtime Library
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
© 2000 Data Device Corporation
All Trademarks are the property of their respective owners
IRIG
MEM
1 OF 4 SHOWN
FIGURE 1. BU-65570V / BU-65572V BLOCK DIAGRAM
MIL-STD-1553A/B BUS
CH A
CH B
BUS LOAD
AND
CONNECTION
RELAYS
Data Device Corporation
www.ddc-web.com
ADDRESS
DATA
VME/VXI
INTERFACE
DSP
2
SYSTEM
BU-65570V/65572V
F-04/05-0
TABLE 1. BU-65570V/72V REQUIREMENTS AND
CAPABILITIES
HARDWARE REQUIREMENTS
• VME or VXI Chassis with Controller Card and one free slot
minimum required, 233 MHz Processor or better recommended.
SOFTWARE REQUIREMENTS
• Windows® 95/98 or Windows NT® or WindRiver VxWorks®II
• DDC’s BU-69068S0 or BUS-69068S2 software diskettes/CD-ROM
AVAILABLE OPERATIONS FOR EACH CHANNEL
• Tests and Simulates MIL-STD-1553 BC and all 31 RT’s
• Provides independent Monitor Mode Operation
• Error injection and Detection
GENERAL
The BU-65570V/72V is DDC’s next generation VME/VXI
Tester/Simulator which can concurrently simulate a MIL-STD-1553
Bus Controller (BC), multiple (up to 31) Remote Terminals (RT’s), and
an intelligent Monitor (MT) simultaneously on all four 1553 buses.
The BU-65570V/72V supports VXI “Plug and Play” installation by
providing the signal MODID at J2. This signal can be enabled by
an on-board jumper to allow the host to signal the card during the
bus enumeration process. If it is not desirable to enable this sig-
nal, the jumper can be removed.
Full error detection features are provided in all modes of operation. In
addition, user specified errors - including bit count, and Manchester II
errors - may be injected in BC and any of the emulated RT modes.
Operational characteristics of the BU-65570V/72V such as
variable output voltage level, bus termination, and coupling
configuration are all software controllable using functions provid-
ed in the software library.
TABLE 2. BU-65570V/65572V SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATING
Supply Voltage
• +5 V
RECEIVER
Threshold Voltage, Transformer
Coupled, Measured on Stub
TRANSMITTER
Differential Output Voltage
BU-65570V (See NOTE 5)
BU-65572V (See NOTES 5 and 6)
POWER SUPPLY REQUIREMENTS
PER 1553 BUS
Voltages/Tolerances
• +5V
Current Drain @ +5.0V
• Idle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
(See NOTE 1)
1553 MESSAGE TIMING
RT Response Time
(See NOTE 2)
BC Intermessage Gap
(See NOTE 3)
BC/RT/MT Response Timeout
(See NOTE 4)
Transmitter Watchdog Timeout
MT Minimum gap for capture
THERMAL
• BU-65570V/72V
Operating Temperature
Storage Temperature
PHYSICAL CHARACTERISTICS
Size “B”
Weight
MIN
TYP
MAX
UNITS
-0.3
7.0
V
0.56
Vp-p
18
0
20
27
21.5
Vp-p
Vp-p
BUS CONTROLLER MODE
The BU-6557VI/72V Bus Controller supports all MIL-STD-1553B
message formats. Up to 1024 unique receive, transmit, mode
code, and RT to RT messages may be defined at one time for
each of the installed channels.
Programmable attributes within a message include time to next
message, bus (channel A or channel B), intermessage routines,
and injected error. The time to next message defines the time
from the start of the present message to the start of the next
message. The time to next message is programmable up to
65,535 msec in 1 µsec increments.
4.5
220
720
870
5.5
240
800
1000
V
mA
mA
mA
10
25
2
668
4
29
µsec
µsec
µsec
µsec
µsec
MINOR AND MAJOR FRAMES
The execution of messages is controlled by a message list
referred to as a frame. The frame specifies the contents and tim-
ing of complete communication runs by the BC. Each entry in the
frame is either a reference to a message or a special frame sym-
bol. The entire frame is referred to as a major frame and is divid-
ed into minor frames each of equal time duration.
The minor frame time is based on a programmable 32-bit
counter with 1 µsec resolution. The BU-65570V/72V supports
major frames of up to 1024 messages per installed channel, with
a period of up to 72 minutes.
0
-40
+55
+85
°C
°C
in
(mm)
oz
(g)
9.2(W) X 6.3(H)
(223.7 X 160)
20.0
(567)
NOTES for TABLE 2:
1. 100% Duty Cycle at MAX Transmit Amplitude [28 Vp-p]
2. This time assumes that this card is not emulating BC.
3. This hardware time is enforced by the firmware. If an attempt to reduce this
time is made, the time will be stretched to 25 µsec.
4. This time is programmable from 2 µsec to 29 µsec in 1 µsec increments.
5. Transformer Coupled, Measured on Stub.
6. Programmable in 1024 steps, within approximate range listed.
BC ERROR INJECTION
Error conditions may be injected on a message by message
basis. The BU-65570V/72V supports three categories of injected
BC Errors: length errors, encoding errors, and gap errors. Length
Errors include both word count errors and bit count errors.
BU-65570V/65572V
F-04/05-0
Data Device Corporation
www.ddc-web.com
3
TABLE 3. J1 - DISCRETE I/O, TRIGGERS, AND IRIG
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DESCRIPTION
+5VDC (fuse protected)
IRIG Mod In
Chassis Ground
Discrete Out 16
Discrete Out 14
Discrete Out 12
Discrete Out 10
Discrete Out 8
Discrete Out 6
Discrete Out 4
Discrete Out 2
Channel 4, BC Trigger Out
Channel 4, BC Trigger In
Channel 3, BC Trigger Out
Channel 3, BC Trigger In
Channel 2, BC Trigger Out
Channel 2, BC Trigger In
Channel 1, BC Trigger Out
PIN
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
DESCRIPTION
Channel 1, BC Trigger In
Chassis Ground
IRIG (Pulse) In
Discrete Out 15
Discrete Out 13
Discrete Out 11
Discrete Out 9
Discrete Out 7
Discrete Out 5
Discrete Out 3
Discrete Out 1
Channel 4, Monitor Trigger Out
Channel 4, Monitor Trigger In
Channel 3, Monitor Trigger Out
Channel 3, Monitor Trigger In
Channel 2, Monitor Trigger Out
Channel 2, Monitor Trigger In
Channel 1, Monitor Trigger Out
Channel 1, Monitor Trigger In
Word Counts of -32 to +1 words may be programmed. Bit counts
of +3, +2, +1, -3, -2, or -1 bit may be programmed on any word
within the message.
Encoding errors are implemented though the use of two simple
yet powerful mechanisms for modifying the output of the BU-
65570V/72V's Manchester encoder. The two modifying functions
are glitch and inverse. A glitch error will force the output of the
encoder to an idle bus condition for the specified period of time.
An inverse error will invert the output of the encoder for the spec-
ified period of time. The word number, starting time, and width
specify the placement of the error. The error may be placed in any
word within the message and its starting time may be pro-
grammed in 500 nsec with a width of up to 3 µsec. This error injec-
tion is capable of generating a host of errors including invalid sync
patterns, parity errors, and Manchester bi-phase errors.
A gap of 3, 4, or 5 µsec (measured mid-parity crossing to mid-sync
crossing) may be inserted between any two words in a message.
This allows for a “dead time” gap between words of 1, 2, or 3 µsec.
executed upon completion of the current message. The user will
define all asynchronous messages after the End-Of-Major frame
symbol and insert the message into the running frame by calling
the insert message routine. The hardware does all of the work.
BC INTERMESSAGE ROUTINES
Upon completion of a BC message, the BU-65570V/72V's on-
board processor will execute up to 2 intermessage routines.
Intermessage routines are used to implement automatic retries
on failed messages as well as other “end of message” functions.
TABLE 5 provides a summary of the BU-65570V/72V's inter-
message routines.
RESPONSE TIMEOUT
The BU-65570V/72V BC, RT's, and MT support programmable response
timeout values ranging from 2 to 29 µsecs in 1 µsec increments.
RT MODE
The BU-65570V/72V can concurrently simulate the operation of
31 unique remote terminals (RT’s) plus a broadcast address for
each of the installed channels. The BU-65570V/72V maintains
31 independent “last status” and “last command” words allowing
for full support of transmit last command and transmit status
BU-65570V/65572V
F-04/05-0
INSERTING ASYNCHRONOUS MESSAGES
The BU-65570V/72V allows an asynchronous message to be
inserted while the card is running. The inserted message will be
Data Device Corporation
www.ddc-web.com
4
TABLE 4. J2 - 1553 BUS 1 & 2 CONNECTOR
PIN
1
2
3
4
5
6
7
8
9
DESCRIPTION
CH1_TXA
CH1_TXA
CH1_TXB
CH1_TXB
GND (connected to shell)
CH2_TXA
CH2_TXA
CH2_TXB
CH2_TXB
TABLE 5. J3 - 1553 BUS 3 & 4 CONNECTOR
PIN
1
2
3
4
5
6
7
8
9
DESCRIPTION
CH3_TXA
CH3_TXA
CH3_TXB
CH3_TXB
GND (connected to shell)
CH4_TXA
CH4_TXA
CH4_TXB
CH4_TXB
mode commands. The BU-65570V/72V supports full RT com-
mand illegalization for each transmit or receive message based
on RT address and sub-address. In addition, individual mode
commands may be illegalized.
RT ERROR INJECTION
Error conditions may be injected on an individual RT/SA basis.
The BU-65570V/72V supports five categories of injected RT
errors: length errors, encoding errors, gap errors, status address
errors, and response errors. Length errors include both word
count errors and bit count errors. Word count errors of -32 to +1
words may be programmed. Bit counts of +3, +2, +1, -3, -2, or -
1 bit may be programmed on any word within the message.
Encoding errors are implemented though the use of two simple
yet powerful mechanisms for modifying the output of the BU-
65570V/72V's Manchester encoder. The two modifying functions
are glitch and inverse. A glitch will force the output of the
encoder to an idle bus condition for the specified period of time.
An inverse will invert the output of the encoder for the specified
period of time. The word number, starting time, and width spec-
ify the placement of this error. The error may be placed in any
word within the message. The starting time is programmed in
500 nsec increments from the beginning of the specified word.
The width of the error is specified in 50 nsec increments up to
3 µsec. This error injection scheme lends itself to generating a
host of errors including invalid sync patterns, parity errors, and
Manchester bi-phase errors.
A gap of 3, 4, or 5 µsec (measured mid parity crossing to mid-sync
crossing) may be inserted between any two words in a message.
This allows for a “dead time” gap between words of 1, 2, or 3 µsec.
A status address error may be injected in which the RT responds
with a status word containing an RT address, which does not
match the terminal's RT address. The RT may be programmed to
respond with any value from zero to 31 in its status response.
The BU-65570V/72V supports three types of response errors: no
response, a late response, or a response on the wrong bus. No
response errors may be programmed for a single bus (Bus A or
Bus B) or for both buses. Injecting a no response error on one
bus provides a simple mechanism for testing bus controller retry
conditions. A late response may be programmed in the range of
2 to 30 µsecs in 1 µsec increments.
RT INTERMESSAGE ROUTINES
The RT section of the BU-65570V/72V also supports intermes-
sage routines. Upon completion of an RT message the BU-
65570V/72V's on-board processor executes two intermessage
routines. The data table that was used by the RT for a given
message specifies which intermessage routines will be execut-
ed. Refer to TABLE 6 for a summary of the BU-65570V/72V's
intermessage routines.
BC/RT DATA TABLES
For each of the installed 1553 channels, the BU-65570V/72V
maintains 1024 data tables within the shared RAM. Each data
table may be up to 32 words in length. These data tables are
common to both BC and RT. Internal lookup tables map each RT
address, T/R, sub-address combination (RT mode) and message
number (BC mode) to a chosen data table. Data tables may be
read or written to in real time by the user and may be either sin-
gle or double buffered. Double buffering can be used to avoid the
memory access contention that occurs when the PC's application
and the 1553 bus access data tables simultaneously. The BU-
65570V/72V provides an optional block data mode in which the
data table number associated with a given BC or RT message is
incremented after completion of the message. The block data
mode is implemented as a circular data structure. Each BC mes-
sage and RT command (RT address, T/R, and sub-address) has
three data table numbers associated with it: first, last, and current.
The current data table number will be incremented after comple-
tion of a message until the value of 'last' is reached, at which point
BU-65570V/65572V
F-04/05-0
Data Device Corporation
www.ddc-web.com
5
