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For Home Electronics and Security Devices Camera Image Processor Series

Camera Image Processor

with ADPCM / MIDI / MP3 /

AAC / HE-AAC Audio

BU6569GVW

●Description

BU6569GVW is a camera image processor with ADPCM/MIDI/MP3/AAC/HE-AAC Audio.

●Features

1) Built-in Camera Module Interface

UXGA size (16001200) for input of image data up to 7.5 fps, SXGA size (12801024) for input of image data up to

15fps and VGA size (640480) for input of image data up to 30fps (zooming function available).

Input data format for YUV=4:2:2, RGB=4:4:4 (8 bits for each RGB).

Filter processing (image processing) to input images (2 gradations / gray scale / sepia / emboss / edge enhancement

/ negative).

Multi-step size reduction down to 1/16 in X- and Y-direction possible, cutting out into an arbitrary size after resizing.

Cut images to be stored into an arbitrary position in frame memory in YUV=4:2:2 format or RGB=5:6:5 format

(16bit/pixel).

2) Built-in frame memory / JPEG code memory

Built in image frame memory (160KB to store 1 frame of 320240@16bit/pixel).

Data to be stored into image frame memory in YUV=4:2:2 format or RGB½5:6:5 format (16bit/pixel).

An arbitrary position of frame memory to be updated to camera image according to mask frame memory.

Mask data to be stored into mask frame memory in 1bit/2pixels in YUV=4:2:2 format or 1bit/1pixels in RGB=5:6:5

format.

Rectangular writing function and rectangular reading function as transparent color to image frame memory.

Frame memory is usable as JPEG code memory (192KB) to store JPEG compressed images.

Frame memory is usable as a ring buffer for JPEG code of 192KB or more.

3) Built-in LCD controller interface

Built-in input/output interface which type is CPU I/F, to LCD controller

For display colors of 262144 colors / 65536 colors / 4096 colors.

Up to 2 LCD module controllers, MAIN and SUB, controllable.

Arbitrary rectangular selection in frame memory to be transferred to LCD controller.

Multi-step scaling process in the range of 1/4 to 2 in X- and Y-direction is available to display images from frame

memory to the LCD.

4) Extended overlay function

Supporting overlay of icon-data up to two icons with LCD data transfer.

Icon-data corresponding to 65536 display colors. Possible to setting transparent colors.

5) Built-in TV encoder interface

Connection to ROHM-made BU9972GU or BU9969KN. Optional rectangular area of frame memory transferable to

TV encoder IC. Multi-step scaling process in the range of 1 to 8 in X- and Y-direction is available for display images

from frame memory to the TV encoder IC.

No.09061EAT04

www.rohm.com

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2009.07 - Rev.A

BU6569GVW

6) Built-in JPEG CODEC

ISO/IEC10918 conforming base line method.

½Compression

For YUV=4:2:2 format only.

Quantization table selectable from 32 built-in tables.

½Decompression

Technical Note

For YUV=4:4:4, 4:2:2(horizontal sub-sampling), 4:2:0, 4:1:1(horizontal sub-sampling), and gray scale.

7) Built-in HOST CPU interface

Adaptable to 16bit bus interface.

Read/Write access to/from frame memory.

Read/Write access to/from internal registers (Indirect access with a index register as the address).

Read/Write access to/from the LCD controller: Parallel/Serial (Direct access available via the LCD interface).

8) Built-in USB interface

USB 2.0 FS adaptable to mass storage class.

9) Built-in NAND Flash memory interface

Adaptable to 8bit and 16bit width for data bus.

ECC calculation by BU6569GVW.

10) Built-in SD card interface

Built-in host controller block of SD card interface, MMC interface.

11) AAC Decode

Supporting Advanced Audio Coding, Low complexity (AAC-LC)

Supporting High Efficiency Advanced Audio Coding (HE-AAC)

12) MP3 Decode

ISO/IEC 11172-3 (32, 44.1 or 48 KHz)

13) Melody source

Simultaneous generation of up to 64 polyphonic tones out of a tone palette of 128 sounds plus 47 drum set sounds,

15 electric drum set sounds, and 32 effect sounds. Up to 8 user customized sound can be used to create original

sounds.

Supporting 12-bit pitch bending and modulation support.

Plays up to four songs simultaneously and supports real-time modification of tempo, key, volume, and pan pot.

14) ADPCM CODEC

Built-in ADPCM decoder/PCM player (2 channels), enables mixing with melody.

Built-in ADPCM encoder/PCM recorder (1 channel).

15) IIS, PCM interface

Digital input

・IIS

interface (IIS, Standard Left Justified format, and Standard Right Justified format)

・PCM

interface (G711.1 u-Law, G711.1 A-Law, Linear (negative number is expressed as 2's-complement.))

Digital output

・IIS

interface (IIS, Standard Left Justified format)

16) Stereo DAC block

Built-in a stereo digital-analog converter.

The DAC block's dynamic range is 1.98 Vpp (typ.)

LPF is included as a smoothing filter subsequent to DAC output, which can eliminate the high-frequency

components of the generated analog waveform.

17) Auto Play

AAC/HE-AAC/MP3 music can be played automatically in SD card or Flash memory of 512B/page and 2KB/page by

using auto play file list (link information of page address) written into Play List RAM by HOST CPU.

18) Clock generation, power management function

Two oscillation circuits configuration by XIN1, 2 and XOUT1, 2 terminals, or clock input available from the XIN1, 2

terminal. Built-in two PLL circuits enable clock multiplication.

Clock control of BU6569GVW inside in unit of block (suspend mode available.)

＊Data

is prepared separately about each register setup. Please refer to the Development Scheme on page 14.

www.rohm.com

2/16

2009.07 - Rev.A

BU6569GVW

Technical Note

System1 (VDDIO1)

P2-P6(D8-D4),P8-P27(D3-D0,ADVB,CSB, WRB,RDB,INT,RESETB,LED0,VIB0,DIGLR,

DIGCK,DACMCK,DIGDIN,DIGDOUT,FSYNC, PCMDIN,DCLK) ,P112-P120(A2,A1,D15-D9)

P42-P43(SD_CLK,SD_CMD),P45-P61(SD_DAT0,FL_CEB,FL_RB,LCDCS1B,

LCDCS2B,LCDWRB,LCDRDB,LCDA0,TEST,LCDD0-LCDD7),

P63-P72(LCDD8-LCDD17),P74-P80(CAMRST,SDA,SDC,CAMCKI,CAMCKO,CAMVS,CAMHS),

P82-P89(CAMD0-CAMD7),P92-P102(TE_VSYNC, TE_HSYNC,TE_PIXCLK,TED0-TED7)

P37-P39(USB_DM,USB_DP,USB_RDY)

P105-P109(XIN1,XOUT1,PLL_FILTER,XIN2,XOUT2)

P29-P30(L_OUT,R_OUT),P34-P35(VREF,MONO_OUT)

System 2 (VDDIO2)

System 3 (VDDIO3)

System 4 (VDDIO4)

System 5 (AVDD)

●Application

Security camera, Intercom with camera, Drive recorder and Web camera etc.

●Lineup

Power source voltage

Parameter

IO1:HOSTI/F

IO2:Camera, LCD

Camera

interface

HOST CPU

interface

LCD

interface

[Image]

Codec

[Sound

/Music]

Multimedia

interface

Package

BU6569GVW

1.7-3.6V(VDDIO1)

2.7-3.6V(VDDIO2) *1

3.0-3.6V(VDDUSB) *2

1.45-1.55V(VDD Core)

Supported up

to 2M pixels.

(1600×1200)

16bit bus

80 systems

CPU

Interface

Supported up

to QVGA

(320×240)

2M pixels JPEG Codec

Motion-JPEG

64MIDI/MP3/AAC

/ HE-AAC decode

ADPCM Codec

USB2.0 FS I/F,

SDC / MMC I/F,

TV encoder I/F,

NAND Flash

Memory I/F

SBGA120W080

*1 VDDIO2, VDDIO4, and AVDD can be used by the same source voltage.

*2 VDDUSB is the same as VDDIO3.

●Absolute

maximum ratings

Parameter

Applied power source

voltage 1 (IO1)

Applied power source

voltage 2 (IO2)

Applied power source

voltage 3 (USB)

Applied power source

voltage 4 (PLL)

Applied power source

voltage 5 (DAC)

Applied power source

voltage 6 (CORE)

Input voltage

Storage

temperature range

Power dissipation

Symbol

VDDIO1

VDDIO2

VDDIO3

VDDIO4

AVDD

VDD

VIN

Tstg

(Ta=25℃)

Rating

-0.3½+4.2

-0.3½+2.1

-0.3½VDDIO+0.3

-40½+150

380

Unit

℃

●Recommended

operating range

Parameter

Applied power source

voltage 1 (IO1）

Applied power source

voltage 2 (IO2）

Applied power source

voltage 3 (USB)

Applied power source

voltage 4 (PLL)

Applied power source

voltage 5 (DAC)

Applied power source

voltage 6 (CORE)

Input voltage range

Operating

temperature range

Symbol

VDDIO1

VDDIO2

VDDIO3

VDDIO4

AVDD

VDD

VIN

Topr

Rating

1.70½3.60 (Typ:3.30V)

2.70½3.60 (Typ: 3.30V)

3.00½3.60 (Typ:3.30V)

2.70½3.60 (Typ: 3.30V)

1.45½1.55 (Typ:1.50V)

0½VDDIO

-30½+85

Unit

℃

＊Please

supply power source in order of VDD→VDDIO.

（VDDIO1→

VDDIO2→ VDDIO3→ VDDIO4→ ADD）

＊Power

dissipation is IC only.

In the case exceeding 25ºC, 3.8mW should be reduced

at the rating 1ºC.

www.rohm.com

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2009.07 - Rev.A

BU6569GVW

●Electric

characteristics

（Unless

otherwise specified, VDD=1.50V,VDDIO1,2,3,4,AVDD=3.30V,GND=0V,Ta=25℃,

fXIN1=12.0MHz,fXIN2=12.0MHz,fAUDIO=74.0MHz,fIMAGE=52.0MHz）

Parameter

Input frequency 1

Input frequency 2

Internal clock frequency 1

Internal clock frequency 2

Operating consumption current 1

Operating consumption current 2

Static consumption current

Input "H" current 1

Input "H" current 2

Input "H" current 3

Input "L" current 1

Input "L" current 2

Input "L" current 3

Input "H" voltage1

Input "L" voltage 1

Input "H" voltage 2

Input "L" voltage 2

Hysteresis voltage width

Input "H" voltage3

Input "L" voltage 3

Differential input sensitivity

Differential common mode

range

Output "H" voltage 1

Output "L" voltage 1

Output "H" voltage 2

Output "L" voltage 2

Output "H" voltage 3

Output "L" voltage 3

Output "H" voltage 4

Output "L" voltage 4

VREF PIN voltage

Analog output voltage range

Analog amplitude

Output load for analog output

Symbol

fXIN1

fXIN2

fIMAGE

fAUDIO

IDD1

IDD2

IDDst

IIH1

IIH2

IIH3

IIL1

IIL2

IIL3

VIH1

VIL1

VIH2

VIL2

Vhys

VIH3

VIL3

VDI

VCM

VOH1

VOL1

VOH2

VOL2

VOH3

VOL3

VOH4

VOL4

VVREF

VAOUT

VAMP

RAOUT

MIN.

2.688

10.0

-10

-160

VDDIO*0.8

-0.3

VDDIO*0.85

-0.3

2.0

0.2

0.8

VDDIO-0.4

0.0

VDDIO-0.4

0.0

VDDIO-0.4

0.0

2.8

0.0

0.475*AVDD

0.47*AVDD

Limits

TYP.

12.8

17.3

-80

0.9

0.5*AVDD

0.6*AVDD

MAX.

26.0

30.0

52.0

74.0

150

100

-25

VDDIO+0.3

VDDIO*0.2

VDDIO+0.3

VDDIO*0.15

0.8

2.5

VDDIO

0.4

VDDIO

0.4

VDDIO

0.4

VDDIO

0.3

0.525*AVDD

0.53*AVDD

Unit

Technical Note

Condition

MHz XIN1 (Duty 50±10%), at PLL ON

MHz XIN2 (Duty 50±10%), at PLL ON

MHz At PLL ON

μA

At Preview operating

At AAC decode operating

（at

44kfs, Auto Play from Flash）

At suspend mode setting

VIH=VDDIO1,2,3,4

Pull-down terminal, VIH=VDDIO2

Pull-up terminal, VIH=VDDIO2

VIL=GND

Pull-down terminal, VIL=GND

Pull-up terminal, VIL=GND

Normal type input

Hysteresis input

VDDIO1(CSB,WRB,RDB)

VDDIO4(XIN1,XIN2)

USB_DP,USB_DM

Single-ended input voltage level

ABS(VUSB_DP-VUSB_DM)

Include VDI range

IOH1=-1.0mA(DC), Normal type output

(Including output mode of I/O terminal)

IOL1=1.0mA(DC), Normal type output

(Including output mode of I/O terminal)

IOH1=-2.0mA(DC), CAMCKO

IOL1=2.0mA(DC), CAMCKO

IOH1=-4.0mA(DC), SD_CLK

IOL1=4.0mA(DC), SD_CLK

IOH1=-2.53mA(DC), USB_DP,USB_DM

IOL1=2.53mA(DC), USB_DP,USB_DM

IOUT=0A(no load),VREF

IOUT=0A(no load). In Silence

VPP Theoretical Value of Dynamic range

KOhm R_OUT,L_OUT,MONO_OUT

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2009.07 - Rev.A

BU6569GVW

●Block

Diagram

VIB0

LED0

SDC/MMC

Interface

Card/MMC

I/F

NAND Flash

Interface

NAND Flash

I/F

Audio

sequencer for

AutoPlay

Out sync

Technical Note

FIFO

2KB

Audio Processor

Audio

path

switch

DAC

Audio Interface

IIS I/F

FIFO

1KB

MIDI engine

FIFO

1KB

ADPCM Codec

PCM I/F

HOST Interface

HOST I/F

LCD control

display data

LCD controller I/F

YUV=4:2:2

RGB=5:6:5

2-line serial

control

2-line type serial

for Camera, TV-

Encoder

YUV=4:2:2

Brightness compenent

D range change

RGB

⇔

YUV

color space conversion

TV Encoderr I/F

TV Encoder

Interface

1/n resizing

cropping

YUV=4:4:4

multistep zoom

Camera

Interface

Max UXGA

(1600×1200)

Image processing

(filter processing)

YUV=4:2:2

JPEG

Codec

Memory

I/F

LCD display frame memory

160KB

Viewing Buffer memory

64KB

Expanded overlay memory

32KB

Mask memory

10KB

Multi step zoom memory

4KB

MIDI engine work memory

Audio Processor work memory

Audio Processor

Sequence Date/

MIDI Wave Data

192KB

Play List

16KB

CAMRST

General purpose

Input/output

Clock control

Power down control

internal clock

USB FS I/F

Interrupt to

HOST

from each blocks

Interrupt controller

PLL

(2 channels)

XIN1,XOUT1

XIN2,XOUT2

RESETB

USB Interface

●Recommended

Application Circuit

Cam era

Ma i n LCD

CAMD[7:0]

SDC

CAMCKI

CAMVS,CAMHS

CAMCKO

SDA

TV -Encoder

TE_PIXCLK

TE_VSYNC

TE_HSYNC

TED[7:0]

LCDCS1B

LCDA0

LCDWRB

LCDRDB

LCDD[15:0]

LCDD[16]

Sub LCD

U SB H os t

USB_DP

USB_DM

LCDD[17]

LCDCS2B

B U6 5 6 9 GVW

AFE

PCMDIN

FSYNC

DCLK

DIGLR

DIGCK

INT

DIGDOUT

RDB

D[15:0]

DIGDIN

CSB

WRB

FL_CEB

FL_RB

NAND

Flash

SD_CLK

SD_CMD

SD_DAT0

LCDD[3:1]

SD C/MMC

H os t CPU

※Data

is prepared separately about each register setup. Please refer to the Development Scheme on page 14.

www.rohm.com

5/16

2009.07 - Rev.A