Intel® Core™ Duo Processor and
Intel® Core™ Solo Processor
on 65 nm Process
Datasheet
September 2006
Document Number: 309221-005
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future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
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product to deviate from published specifications. Current characterized errata are available on request.
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Copyright © 2006, Intel Corporation. All rights reserved.
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Datasheet
Contents
1
Introduction
.............................................................................................................. 7
1.1
Terminology ....................................................................................................... 9
1.2
References ......................................................................................................... 9
Low Power Features
................................................................................................ 11
2.1
Clock Control and Low Power States .................................................................... 11
2.1.1 Core Low-Power States ........................................................................... 13
2.1.1.1 C0 State .................................................................................. 13
2.1.1.2 C1/AutoHALT Powerdown State .................................................. 13
2.1.1.3 C1/MWAIT Powerdown State ...................................................... 13
2.1.1.4 Core C2 State........................................................................... 13
2.1.1.5 Core C3 State........................................................................... 14
2.1.1.6 Core C4 State........................................................................... 14
2.1.2 Package Low Power States ...................................................................... 14
2.1.2.1 Normal State............................................................................ 14
2.1.2.2 Stop-Grant State ...................................................................... 14
2.1.2.3 Stop Grant Snoop State ............................................................. 15
2.1.2.4 Sleep State .............................................................................. 15
2.1.2.5 Deep Sleep State ...................................................................... 16
2.1.2.6 Deeper Sleep State ................................................................... 16
2.2
Enhanced Intel SpeedStep® Technology .............................................................. 17
2.3
Extended Low Power States ................................................................................ 18
2.4
FSB Low Power Enhancements ............................................................................ 19
2.5
Processor Power Status Indicator (PSI#) Signal..................................................... 19
Electrical Specifications
........................................................................................... 21
3.1
Power and Ground Pins ...................................................................................... 21
3.2
FSB Clock (BCLK[1:0]) and Processor Clocking ...................................................... 21
3.3
Voltage Identification ......................................................................................... 21
3.4
Catastrophic Thermal Protection .......................................................................... 24
3.5
Signal Terminations and Unused Pins ................................................................... 25
3.6
FSB Frequency Select Signals (BSEL[2:0])............................................................ 25
3.7
FSB Signal Groups............................................................................................. 25
3.8
CMOS Signals ................................................................................................... 27
3.9
Maximum Ratings.............................................................................................. 27
3.10 Processor DC Specifications ................................................................................ 28
Package Mechanical Specifications and Pin Information
.......................................... 43
4.1
Package Mechanical Specifications ....................................................................... 43
4.1.1 Package Mechanical Drawings .................................................................. 43
4.1.2 Processor Component Keep-Out Zones ...................................................... 48
4.1.3 Package Loading Specifications ................................................................ 48
4.1.4 Processor Mass Specifications .................................................................. 48
4.2
Processor Pinout and Pin List .............................................................................. 49
4.3
Alphabetical Signals Reference ............................................................................ 51
Thermal Specifications and Design Considerations
.................................................. 81
5.1
Thermal Specifications ....................................................................................... 87
5.1.1 Thermal Diode ....................................................................................... 87
5.1.2 Thermal Diode Offset .............................................................................. 89
5.1.3 Intel
®
Thermal Monitor ........................................................................... 89
5.1.4 Digital Thermal Sensor (DTS)................................................................... 91
5.1.5 Out of Specification Detection .................................................................. 92
2
3
4
5
Datasheet
3
5.1.6
PROCHOT# Signal Pin .............................................................................92
Figures
1
2
3
4
5
6
7
8
9
10
Package-Level Low Power States ................................................................................12
Core Low Power States..............................................................................................12
Active VCC and ICC Load Line for Intel Core Duo Processor (SV, LV & ULV) and
Intel Core Solo Processor SV ......................................................................................36
Deeper Sleep VCC and ICC Load Line for Intel Core Duo Processor (SV, LV & ULV)
and Intel Core Solo Processor SV ................................................................................37
Active VCC and ICC Load Line for Intel Core Solo Processor ULV .....................................38
Deeper Sleep VCC and ICC Load Line for Intel Core Solo Processor ULV ...........................39
Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ................................................44
Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) ................................................45
Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) ................................................46
Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) ...............................................47
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Coordination of Core-Level Low Power States at the Package Level .................................11
Voltage Identification Definition ..................................................................................21
BSEL[2:0] Encoding for BCLK Frequency......................................................................25
FSB Pin Groups ........................................................................................................26
Processor DC Absolute Maximum Ratings.....................................................................27
Voltage and Current Specifications for Intel Core Duo Processor SV (Standard Voltage) .....28
Voltage and Current Specifications for Intel Core Solo Processor SV (Standard Voltage) .....30
Voltage and Current Specifications for Intel Core Duo Processor LV (Low Voltage) .............31
Voltage and Current Specifications Intel Core Duo Processor Ultra Low Voltage (ULV) ........33
Voltage and Current Specifications for Intel Core Solo Processor ULV (Ultra Low Voltage) ...35
FSB Differential BCLK Specifications ............................................................................40
AGTL+ Signal Group DC Specifications ........................................................................40
CMOS Signal Group DC Specifications..........................................................................41
Open Drain Signal Group DC Specifications ..................................................................41
The Coordinates of the Processor Pins as Viewed from the Top of the Package
(Sheet 1 of 2) ..........................................................................................................49
The Coordinates of the Processor Pins as Viewed from the Top of the Package
(Sheet 2 of 2) ..........................................................................................................50
Signal Description.....................................................................................................51
Pin Listing by Pin Name .............................................................................................61
Pin Listing by Pin Number ..........................................................................................71
Power Specifications for the Intel Core Duo Processor SV (Standard Voltage) ...................82
Power Specifications for the Intel Core Solo Processor SV (Standard Voltage) ...................83
Power Specifications for the Intel Core Duo Processor LV (Low Voltage) ...........................84
Power Specifications for the Intel Core Duo Processor, Ultra Low Voltage (ULV) ................85
Power Specifications for the Intel Core Solo Processor ULV (Ultra Low Voltage) .................86
Thermal Diode Interface ............................................................................................87
Thermal Diode Parameters using Diode Mode ...............................................................88
Thermal Diode Parameters using Transistor Mode .........................................................88
Thermal Diode n
trim
and Diode Correction Toffset..........................................................89
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Datasheet
Revision History
Revision
-001
Initial Release
•
•
•
•
-002
Added references to ULV processor throughout the document
Replaced references to the terminology Deep C4 voltage with Intel® Enhanced Deeper
Sleep Voltage throughout the document.
Replaced references to Enhanced Low Power states with CxE Low Power States
Section 3.10
— Included
Table 10
Voltage and Current Specifications for Intel Core Solo Processor
ULV
— Included
Figure 5
Active VCC and ICC Load Line for Intel Core Solo Processor ULV
— Included
Figure 6
Deeper Sleep VCC and ICC Load Line for Intel Core Solo
Processor ULV
Chapter 5
— Included
Table 24
Power Specifications for the Intel Core Solo Processor ULV (Ultra
Low Voltage)
Added Intel® Core™ Duo Processor T2300E and Intel® Core™ Solo Processor T1400
specifications.
Added references to Intel Core Duo Processor, Ultra Low Voltage (ULV) throughout the
document
CxE low power states now also referred to as Extended Low Power States
Section 3.10
— Updated
Table 6
- Added Icc spec for T2700
— Included
Table 9
Voltage and Current Specifications Intel Core Duo Processor, Ultra
Low Voltage (ULV)
Chapter 5
— Updated
Table 20
- Added TDP for T2700
— Included
Table 23
- Power Specification for Intel Core Duo Processor Ultra Low
Voltage (ULV)
In
Chapter 3:
— Added L2500 processor specifications to
Table 8.
— Added U2400 processor specifications to
Table 9.
In
Chapter 5:
— Added L2500 processor power specifications to
Table 22.
— Added U2400 processor power specifications to
Table 23.
Description
Date
January 2006
April 2006
•
-003
•
•
•
•
May 2006
-004
•
June 2006
•
-005
•
September 2006
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Datasheet
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