Intel® Xeon® Processor E5-2400
Product Family
Datasheet - Volume One
May 2012
Reference Number: 327248-001
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Intel® Xeon® Processor E5-2400 Product Family
Datasheet Volume One
Table of Contents
1
Overview
................................................................................................................. 13
1.1
Introduction ..................................................................................................... 13
1.1.1 Processor Feature Details ........................................................................ 13
1.1.2 Supported Technologies .......................................................................... 14
1.2
Interfaces ........................................................................................................ 14
1.2.1 System Memory Support ......................................................................... 14
1.2.2 PCI Express* ......................................................................................... 15
1.2.3 Direct Media Interface Gen 2 (DMI2)......................................................... 17
1.2.4 Intel® QuickPath Interconnect (Intel® QPI) .............................................. 17
1.2.5 Platform Environment Control Interface (PECI) ........................................... 18
1.3
Power Management Support ............................................................................... 18
1.3.1 Processor Package and Core States........................................................... 18
1.3.2 System States Support ........................................................................... 18
1.3.3 Memory Controller.................................................................................. 18
1.3.4 PCI Express ........................................................................................... 19
1.3.5 Intel QuickPath Interconnect.................................................................... 19
1.4
Thermal Management Support ............................................................................ 19
1.5
Package Summary............................................................................................. 19
1.6
Terminology ..................................................................................................... 19
1.7
Related Documents ........................................................................................... 22
1.8
State of Data .................................................................................................... 23
Interfaces................................................................................................................
25
2.1
System Memory Interface .................................................................................. 25
2.1.1 System Memory Technology Support ........................................................ 25
2.1.2 System Memory Timing Support............................................................... 25
2.2
PCI Express* Interface....................................................................................... 26
2.2.1 PCI Express* Architecture ....................................................................... 26
2.2.1.1 Transaction Layer ..................................................................... 27
2.2.1.2 Data Link Layer ........................................................................ 27
2.2.1.3 Physical Layer .......................................................................... 27
2.2.2 PCI Express* Configuration Mechanism ..................................................... 27
2.3
DMI2/PCI Express* Interface .............................................................................. 28
2.3.1 DMI2 Error Flow ..................................................................................... 28
2.3.2 Processor/PCH Compatibility Assumptions.................................................. 28
2.3.3 DMI2 Link Down..................................................................................... 28
2.4
Intel QuickPath Interconnect............................................................................... 28
2.5
Platform Environment Control Interface (PECI) ...................................................... 31
2.5.1 PECI Client Capabilities ........................................................................... 31
2.5.1.1 Thermal Management................................................................ 32
2.5.1.2 Platform Manageability .............................................................. 32
2.5.1.3 Processor Interface Tuning and Diagnostics .................................. 32
2.5.2 Client Command Suite ............................................................................ 32
2.5.2.1 Ping()...................................................................................... 32
2.5.2.2 GetDIB() ................................................................................. 33
2.5.2.3 GetTemp() ............................................................................... 35
2.5.2.4 RdPkgConfig() .......................................................................... 36
2.5.2.5 WrPkgConfig().......................................................................... 37
2.5.2.6 Package Configuration Capabilities .............................................. 39
2.5.2.7 RdIAMSR()............................................................................... 61
2.5.2.8 RdPCIConfig() .......................................................................... 65
2.5.2.9 RdPCIConfigLocal() ................................................................... 66
2.5.2.10 WrPCIConfigLocal() ................................................................... 68
2.5.3 Client Management................................................................................. 70
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Datasheet Volume One
3
2.5.4
2.5.5
2.5.6
2.5.7
2.5.3.1 Power-up Sequencing ................................................................70
2.5.3.2 Device Discovery.......................................................................71
2.5.3.3 Client Addressing ......................................................................71
2.5.3.4 C-states ...................................................................................72
2.5.3.5 S-states ...................................................................................73
2.5.3.6 Processor Reset ........................................................................73
2.5.3.7 System Service Processor (SSP) Mode Support..............................73
2.5.3.8 Processor Error Handling ............................................................74
2.5.3.9 Originator Retry and Timeout Policy .............................................74
2.5.3.10 Enumerating PECI Client Capabilities............................................75
Multi-Domain Commands .........................................................................75
Client Responses ....................................................................................76
2.5.5.1 Abort FCS ................................................................................76
2.5.5.2 Completion Codes .....................................................................76
Originator Responses ..............................................................................77
DTS Temperature Data ............................................................................77
2.5.7.1 Format ....................................................................................77
2.5.7.2 Interpretation ...........................................................................77
2.5.7.3 Temperature Filtering ................................................................78
2.5.7.4 Reserved Values .......................................................................78
3
Technologies............................................................................................................79
3.1
Intel® Virtualization Technology (Intel® VT) .........................................................79
3.1.1 Intel VT-x Objectives...............................................................................79
3.1.2 Intel VT-x Features .................................................................................80
3.1.3 Intel VT-d Objectives...............................................................................80
3.1.3.1 Intel VT-d Features Supported ....................................................80
3.1.4 Intel Virtualization Technology Processor Extensions....................................81
3.2
Security Technologies.........................................................................................81
3.2.1 Intel® Trusted Execution Technology ........................................................81
3.2.2 Intel Trusted Execution Technology – Server Extensions ..............................82
3.2.3 Intel® Advanced Encryption Standard Instructions (Intel® AES-NI) ..............82
3.2.4 Execute Disable Bit .................................................................................83
3.3
Intel® Hyper-Threading Technology .....................................................................83
3.4
Intel® Turbo Boost Technology ...........................................................................83
3.4.1 Intel® Turbo Boost Operating Frequency ...................................................83
3.5
Enhanced Intel SpeedStep® Technology ...............................................................84
3.6
Intel® Intelligent Power Technology.....................................................................84
3.7
Intel® Advanced Vector Extensions (Intel® AVX) ..................................................84
3.8
Intel® Dynamic Power Technology (Intel® DPT)....................................................85
Power Management
.................................................................................................87
4.1
ACPI States Supported .......................................................................................87
4.1.1 System States........................................................................................87
4.1.2 Processor Package and Core States ...........................................................87
4.1.3 Integrated Memory Controller States .........................................................88
4.1.4 DMI2/PCI Express* Link States.................................................................89
4.1.5 Intel QuickPath Interconnect States ..........................................................89
4.1.6 G, S, and C State Combinations................................................................89
4.2
Processor Core/Package Power Management .........................................................90
4.2.1 Enhanced Intel SpeedStep Technology.......................................................90
4.2.2 Low-Power Idle States.............................................................................90
4.2.3 Requesting Low-Power Idle States ............................................................91
4.2.4 Core C-states .........................................................................................92
4.2.4.1 Core C0 State ...........................................................................92
4.2.4.2 Core C1/C1E State ....................................................................92
4.2.4.3 Core C3 State ...........................................................................93
4.2.4.4 Core C6 State ...........................................................................93
4.2.4.5 Core C7 State ...........................................................................93
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Datasheet Volume One
4.3
4.4
5
4.2.4.6 C-State Auto-Demotion ............................................................. 93
Package C-States ................................................................................... 94
4.2.5.1 Package C0 .............................................................................. 95
4.2.5.2 Package C1/C1E ....................................................................... 95
4.2.5.3 Package C2 State...................................................................... 96
4.2.5.4 Package C3 State...................................................................... 96
4.2.5.5 Package C6 State...................................................................... 96
4.2.6 Package C-State Power Specifications ....................................................... 97
System Memory Power Management.................................................................... 97
4.3.1 CKE Power-Down ................................................................................... 98
4.3.2 Self Refresh........................................................................................... 98
4.3.2.1 Self Refresh Entry ..................................................................... 98
4.3.2.2 Self Refresh Exit ....................................................................... 98
4.3.2.3 DLL and PLL Shutdown .............................................................. 98
4.3.3 DRAM I/O Power Management ................................................................. 99
DMI2/PCI Express* Power Management ............................................................... 99
4.2.5
Thermal Management Specifications......................................................................
101
5.1
Package Thermal Specifications ......................................................................... 101
5.1.1 Thermal Specifications .......................................................................... 101
5.1.2 TCASE and DTS Based Thermal Specifications .......................................... 102
5.1.2.1 95W Thermal Specifications...................................................... 103
5.1.2.2 80W Thermal Specifications...................................................... 107
5.1.2.3 70W Thermal Specifications...................................................... 112
5.1.2.4 60W Thermal Specification ....................................................... 115
5.1.2.5 50W 8-Core Thermal Specification............................................. 118
5.1.2.6 50W 4-Core Thermal Specification............................................. 120
5.1.3 Embedded Server Thermal Profiles ......................................................... 122
5.1.3.1 Embedded LV70W-8C Thermal Specifications.............................. 122
5.1.3.2 Embedded LV60W-6C Thermal Specifications.............................. 125
5.1.3.3 Embedded LV50W-4C Thermal Specifications.............................. 127
5.1.3.4 Storage SKU LV40W-24C Thermal Specifications ......................... 129
5.1.4 Thermal Metrology ............................................................................... 131
5.2
Processor Core Thermal Features....................................................................... 133
5.2.1 Processor Temperature ......................................................................... 133
5.2.2 Adaptive Thermal Monitor...................................................................... 133
5.2.2.1 Frequency/SVID Control .......................................................... 134
5.2.2.2 Clock Modulation .................................................................... 135
5.2.3 On-Demand Mode ................................................................................ 135
5.2.4 PROCHOT_N Signal .............................................................................. 135
5.2.5 THERMTRIP_N Signal ............................................................................ 136
5.2.6 Integrated Memory Controller (IMC) Thermal Features .............................. 136
5.2.6.1 DRAM Throttling Options.......................................................... 136
5.2.6.2 Hybrid Closed Loop Thermal Throttling (CLTT_Hybrid) ................. 137
5.2.6.3 MEM_HOT_C1_N and MEM_HOT_C23_N Signal ........................... 137
5.2.6.4 Integrated Dual SMBus Master Controllers for SMI....................... 137
Signal Descriptions
................................................................................................ 139
6.1
System Memory Interface Signals...................................................................... 139
6.2
PCI Express* Based Interface Signals................................................................. 140
6.3
DMI2/PCI Express* Port 0 Signals ..................................................................... 141
6.4
Intel QuickPath Interconnect Signals.................................................................. 142
6.5
PECI Signal .................................................................................................... 142
6.6
System Reference Clock Signals ........................................................................ 142
6.7
JTAG and TAP Signals ...................................................................................... 143
6.8
Serial VID Interface (SVID) Signals.................................................................... 143
6.9
Processor Asynchronous Sideband and Miscellaneous Signals ................................ 143
6.10 Processor Power and Ground Supplies ................................................................ 146
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Intel® Xeon® Processor E5-2400 Product Family
Datasheet Volume One
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