Intel® Xeon® Processor E5 Product
Family
Datasheet- Volume Two
May 2012
Reference Number: 326509-002
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I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed
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2
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2
Intel® Xeon® Processor E5 Product Family
Datasheet Volume 2
Contents
1
Introduction
.............................................................................................................. 9
1.1
Document Terminology ........................................................................................ 9
1.2
Related Documents ........................................................................................... 12
1.3
Register Terminology ......................................................................................... 12
Configuration Process and Registers
....................................................................... 15
2.1
Platform Configuration Structure ......................................................................... 15
2.1.1 Processor IIO Devices (CPUBUSNO (0))..................................................... 15
2.1.2 Processor Uncore Devices (CPUBUSN0 (1)) ................................................ 17
2.2
Configuration Register Rules ............................................................................... 18
2.2.1 CSR Access ........................................................................................... 18
2.2.2 PCI Bus Number..................................................................................... 18
2.2.3 Uncore Bus Number................................................................................ 19
2.3
Configuration Mechanisms .................................................................................. 19
2.3.1 Standard PCI Express* Configuration Mechanism........................................ 19
2.4
Device Mapping................................................................................................. 19
Processor Integrated I/O (IIO) Configuration Registers
......................................... 23
3.1
Processor IIO Devices (PCI Bus CPUBUSNO (0)) .................................................... 23
3.2
PCI Configuration Space Registers (CSRs)......................................................
23
3.2.1 Unimplemented Devices/Functions and Registers........................................ 23
3.2.2 IIO Registers Specific to Intel® Xeon® Processor E5 Product Family ............. 23
3.2.3 PCI Bus Number..................................................................................... 23
3.2.4 IIO PCI Express Configuration Space Registers ........................................... 26
3.2.5 Standard PCI Configuration Space (Type 0/1 Common Configuration Space) .. 32
3.2.6 PCI Express and DMI2 Error Registers ....................................................... 95
3.2.7 PCI Express Lane Equalization Registers .................................................. 106
3.2.8 DMI Root Complex Register Block (RCRB)................................................ 111
3.3
Non Transparent Bridge Registers...................................................................... 120
3.3.1 Configuration Register Map (NTB Primary Side) ........................................ 120
3.3.2 Standard PCI Configuration Space - Type 0 Common Configuration Space.... 122
3.3.3 NTB Port 3A Configured as Primary Endpoint Device.................................. 129
3.3.4 PCI Express Configuration Registers (NTB Secondary Side) ........................ 165
3.3.5 Configuration Register Map (NTB Secondary Side) .................................... 165
3.3.6 NTB Shadowed MMIO Space .................................................................. 193
3.3.7 NTB Primary/Secondary Host MMIO Registers .......................................... 194
3.3.8 MSI-X MMIO Registers (NTB Primary side) ............................................... 210
3.3.9 MSI-X MMIO registers (NTB Secondary Side) ........................................... 212
3.4
Intel® QuickData Technology ........................................................................... 214
3.4.1 Intel® QuickData Technology Registers Maps........................................... 214
3.4.2 Intel® QuickData Technology Registers Definitions ................................... 217
3.4.3 Intel® QuickData Technology MMIO Registers Map ................................... 236
3.4.4 Intel® QuickData Technology MMIO Registers Definitions .......................... 238
3.4.5 DMA Channel Specific Registers.............................................................. 245
3.5
Integrated I/O Core Registers ........................................................................... 254
3.5.1 Configuration Register Maps (Device 5, Function: 0, 2 and 4) ..................... 255
3.5.2 PCI Configuration Space Registers Common to Device 5 ............................ 264
3.5.3 Intel VT-d, Address Mapping, System Management,
Coherent Interface, Misc Registers.......................................................... 269
3.5.4 Global System Control and Error Registers............................................... 300
3.5.5 Local Error Registers............................................................................. 311
3.5.6 IOxAPIC PCI Configuration Space ........................................................... 325
3.5.7 I/OxAPIC Memory Mapped Registers ....................................................... 332
2
3
Intel® Xeon® Processor E5 Product Family
Datasheet Volume 2
3
3.5.8
4
Intel VT-d Memory Mapped Register ........................................................ 339
Processor Uncore Configuration Registers
............................................................. 381
4.1
PCI Standard Registers..................................................................................... 381
4.1.1 VID: Vendor Identification ..................................................................... 381
4.2
Intel QuickPath Interconnect Register ................................................................. 385
4.2.1 Intel Xeon Processor E5-2600 Product Family Registers ............................. 386
4.2.2 CSR Register Maps................................................................................ 386
4.2.3 Intel QuickPath Interconnect Link Layers Registers.................................... 388
4.3
CBo Registers.................................................................................................. 388
4.3.1 CSR Register Maps................................................................................ 388
4.4
Integrated Memory Controller Configuration Registers .......................................... 392
4.4.1 Intel Xeon Processor E5-1600 E5-2600 and E5-4600 Processor Registers ..... 393
4.4.2 Intel Xeon Processor E5-2400 Processor Registers..................................... 393
4.4.3 CSR Register Maps................................................................................ 393
4.4.4 Integrated Memory Controller Target Address Registers ............................. 403
4.4.5 Integrated Memory Controller MemHot Registers ...................................... 407
4.4.6 Integrated Memory Controller SMBus Registers......................................... 412
4.4.7 Integrated Memory Controller RAS Registers ............................................ 420
4.4.8 Integrated Memory Controller DIMM Memory Technology Type Registers...... 426
4.4.9 Integrated Memory Controller Error Injection Registers .............................. 428
4.4.10 Integrated Memory Controller Thermal Control Registers............................ 428
4.4.11 Integrated Memory Controller DIMM Channels Timing Registers .................. 434
4.4.12 Integrated Memory Controller Error Registers ........................................... 444
4.5
Intel Xeon Processor E5 Product Family Home Agent Registers............................... 451
4.5.1 CSR Register Maps................................................................................ 451
4.5.2 Intel Xeon Processor E5 Product Family Home Agent Register ..................... 452
4.6
Power Control Unit (PCU) Registers .................................................................... 452
4.6.1 CSR Register Maps................................................................................ 452
4.6.2 PCU0 Registers..................................................................................... 455
4.6.3 PCU1 Registers..................................................................................... 459
4.6.4 PCU2 Registers..................................................................................... 461
4.6.5 PCU3 Registers..................................................................................... 464
4.7
Processor Utility Box (UBOX) Registers ............................................................... 464
4.7.1 CSR Group........................................................................................... 464
4.7.2 Processor Utility Box (UBOX) Registers .................................................... 466
4.7.3 ScratchPad and Semaphore Registers ...................................................... 469
4.8
Performance Monitoring (PMON) Registers .......................................................... 470
4.8.1 CSR Register Maps................................................................................ 470
4.8.2 Processor Performance Monitor Registers ................................................. 471
4.9
R2PCIe Routing Table and Ring Credits ............................................................... 474
4.9.1 R2PCIe Routing Register Map ................................................................. 474
4.10 MISC Registers................................................................................................ 475
4.10.1 QPIREUT_PM_R0: REUT Power Management Register 0.............................. 475
4.10.2 FWDC_LCPKAMP_CFG ........................................................................... 477
2-1
2-2
3-1
3-2
Processor Integrated I/O Device Map....................................................................15
Processor Uncore Devices Map.............................................................................17
DMI2 Port (Device 0) and PCI Express* Root Ports Type 1 Configuration Space ..........24
Device 0 (PCIe mode), Device 1/Functions 0-1 (Root Ports),
Device 2/Function 0-3 (Root Port Mode) and Devices 3/
Functions 0-3 (Root Ports) Type 1 Configuration Space ...........................................25
Base Address of Intel VT-d Remap Engines.......................................................... 339
Figures
3-3
4
Intel® Xeon® Processor E5 Product Family
Datasheet Volume 2
Tables
1-1
1-2
1-3
2-1
3-1
3-2
3-3
3-4
Processor Terminology ......................................................................................... 9
Referenced Documents ...................................................................................... 12
Register Attributes Definitions ............................................................................. 12
Functions Specifically Handled by the Processor..................................................... 19
(DMI2 Mode) Legacy Configuration Map. Device 0 Function 0 -Offset 0x00h-0x0FCh... 26
(DMI2) Extended Configuration Map. Device 0/Function 0 -Offset 0x100-0x1FCh ....... 27
(DMI2) Mode Extended Configuration Map. Device 0/Function 0 -
Offset 0x200h-0x2FCh ....................................................................................... 28
Device 0/Function 0 (PCIe* Root Port Mode), Device 1/Functions 0-1
(PCIe Root Ports), Devices 2/Functions 0-3 (PCIe Root Ports) and
Device 3/Function 0-3 (PCIe Root Ports) Legacy Configuration Map .......................... 28
Device 0/Function 0 (PCIe Root Port Mode), Device 1/Functions 0-1
(PCIe Root Ports), Devices 2/Functions 0-3 (PCIe Root Ports) and
Device 3/Function 0-3 (PCIe Root Ports) Extended
Configuration Map 100 - 0x1FFh.......................................................................... 30
Device 0/Function 0 (PCIe Root Port Mode), Device 1/Functions 0-1
(PCIe Root Ports), Devices 2/Functions 0-3 (PCIe Root Ports) and
Device 3/Function 0-3 (PCIe Root Ports) Extended Configuration
Map - Offset 0x200-0x2FCh ................................................................................ 31
DMI2 RCRB Registers....................................................................................... 111
Device 3 Function 0 (Non-Transparent Bridge) Configuration
Map Offset 0x00h - 0xFCh ................................................................................ 120
Device 3 Function 0 (Non-Transparent Bridge) Configuration
Map Offset 0x100h - 0x1FCh............................................................................. 121
Device 3 Function 0 (Non-Transparent Bridge) Configuration
Map Offset 0x200h - 0x2FCh............................................................................. 122
Device 0 Function 0 (Non -Transparent Bridge) Configuration Map 0x00h - 0xFCh .... 165
Device 0 Function 0 (Non -Transparent Bridge) Configuration Map 0x100h - 0x1FCh 166
NTB MMIO Shadow Registers ............................................................................ 193
NTB MMIO Map ............................................................................................... 193
NTB MMIO Map ............................................................................................... 210
MSI-X Vector Handling and Processing by IIO on Primary Side............................... 211
NTB MMIO Map ............................................................................................... 212
MSI-X Vector Handling and Processing by IIO on Secondary Side........................... 214
Intel® QuickData Technology Configuration Map. Device 4
Function 0 -7 Offset 0x00H to 0x0FCH ............................................................... 214
Intel® QuickData Technology Configuration Map. Device 4
Function 0 -7 Offset 0x100-0x1FF...................................................................... 216
Intel® QuickData Technology CB_BAR Registers
(Replicated for Each CB_BAR[0:7]) .................................................................... 236
Intel® QuickData Technology CB_BAR Registers
(Replicated for Each CB_BAR[0:7]) .................................................................... 237
Intel® QuickData Technology CB_BAR MMIO Registers
(replicated for each CB_BAR[7:0]) - Offset 0x2000-0x20FF................................... 238
DMA Memory Mapped Register Set Locations ...................................................... 239
Intel VT, Address Map, System Management, Miscellaneous
Registers (Device 5, Function 0) - Offset 0x000-0x0FF ......................................... 255
Intel VT-d, Address Map, System Management,
Miscellaneous Registers (Device 5, Function 0) - Offset 0x100-0x1FF ..................... 256
Intel VT-d, Address Map, System Management,
Miscellaneous Registers (Device 5, Function 0) - Offset 0x200-0x2FF ..................... 256
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
Intel® Xeon® Processor E5 Product Family
Datasheet Volume 2
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