ClassⅠ(NP0) General
Multilayer Ceramic Chip Capacitors
ClassⅠ(NP0)
General Multilayer Ceramic Chip Capacitors
■
Product Features And Application
Various kinds of dimensions, All kinds of series temperature coefficient, Stable performance.
Suited for resonant circuit application where low losses and high stability of capacitance are
essential or where a precisely defined temperature coefficient is required.
■
Part Numbering
C
①
0805
②
CG
③
101
④
J
⑤
500
⑥
W
⑦
T
⑧
General Ceramic
Chip Capacitor
①
Chip
Dimensions Temperature Rated Tolerance
Coefficient Capacitance
Rated Termination Packing
Voltage Type
Code
capacitor code
Code
C
Ceramic chip capacitors
General
②
Dimensions
Dimensions（Unit：mm）
Code
0402
0603
0805
1206
1210
1812
L
1.0 ± 0.05
1.6 ± 0.1
2.0 ± 0.2
3.2 ± 0.2
3.2 ± 0.2
4.5 ± 0.3
W
0.5 ± 0.05
0.80 ± 0.1
1.25 ± 0.2
1.6 ± 0.2
2.5 ± 0.2
3.2 ± 0.2
T(max)
0.5 ± 0.05
0.8 ± 0.1
1.40
1.40
1.70
2.0
B(min)
0.2
0.20
0.25
0.25
0.25
0.45
B(max)
0.3
0.71
0.76
0.76
0.76
1.0
③
Temperature
Coefficient
Temperature Coefficient
0 ± 30ppm/℃
-33 ± 30ppm/℃
-75 ± 30ppm/℃
-150 ± 60ppm/℃
-220 ± 60ppm/℃
-330 ± 60ppm/℃
-470 ± 60ppm/℃
-750 ± 120ppm/℃
+350½-1000ppm/℃
Operating Temperature Range
Code(EIA)
CG (C0G)
HG (H2G)
LG (L2G)
PH (P2H)
RH (R2H)
SH (S2H)
TH (T2H)
UJ (U2J)
SL
-55℃½+125℃
ClassⅠ(NP0) General
Multilayer Ceramic Chip Capacitors
④
Rated capacitance
Codee
1R5
101
222
⑤
Tolerance
Code
B
C
D
F
G
J
⑥
Rated Voltage
Code
250
500
101
201
⑦
Terminations Type
Code
W
P
⑧
Packaging Type
Code
T
B
Packaging Type
Tape carrier packaging
Bulk packaging in a bag
Terminations Type
Nickel、Plated Pb/Sn
Silver Palladium Termination
Rated Voltage（DC）
25V
50V
100V
200V
Tolerance
± 0.1 pF
± 0.25 pF
± 0.5 pF
±1%
±2%
±5 %
Capacitance Range
＜10pF
Capacitance
1.5pF
100pF
22000pF
≥10pF
ClassⅠ(NP0) General
Multilayer Ceramic Chip Capacitors
■
Rated Capacitance Rage Table
T.C.
Dime-
nsions
0402
0603
100V
SL
NTC
50V
0805
100V
50V
1206
100V
25V
0402
50V
25V
0603
50V
100V
50V
0805
100V
200V
25V
C0G
50V
1206
100V
200V
50V
1210
100V
200V
50V
1812
100V
200V
470
1000
1000
36000
16000
560
2200
4700
2200
47000
18000
8200
68000
5100
560
1500
10000
27
2200
1200
150
1000
1000
150
3300
1000
6800
680
2700
Volt.
50V
50V
0.5
10
Capacitance Rage(pF)
100
1000
220
1000
10000
ClassⅠ(NP0) General
Multilayer Ceramic Chip Capacitors
■
Characteristics Curve
●Capacitance
Change vs Aging
●
Capacitance vs Temperature
●
Capacitance Change vs AC Voltage
Capacitance Change (%)
Measuring condition 1MHz
Capacitance Change (%)
AC Voltage (Vrms)
Capacitance Change (%)
C0G
HG
LG
PH
RH
SH
TH
UJ
Time (hour)
●
Capacitance Change vs DC Voltage
Measuring condition 1MHz
Capacitance Change (%)
DC Voltage (VDC)
●Impedance
vs Frequency
Impedance (
Ω
)
Frequency (Hz)
ClassⅠ(NP0) General
Multilayer Ceramic Chip Capacitors
■
Specifications
No
1
Item
Operating
Temperature
Range
Rated
Voltage
Appearance
Dimensions
Dielectric
Strength
Insulation
Resistance
Capacitance
Q/(D.F.)
Dissipation
Factor
and Test Methods
Specification
-55℃½+125℃
The rated voltage means the maximum direct voltage or peak
value of pulse voltage which may be applied continuously to
a capacitor.
Visual inspection
Callipers inspection
No failure shall be observed when 250% of the rated voltage
is applied between the terminations for 1 to 5 seconds,
provided the charge/discharge current is less than 50mA.
The insulation resistance shall be measured with the
following voltage at normal temperature and humidity and
within 1 minute of charging.
The capacitance/Q/D.F. shall be measured at 25℃ with the
frequency and voltage shown in the table.
Item
Frequency
Voltage
C＜1000pF
1±0.1MHz
1±0.2Vrms
C≥1000pF
1±0.1KHz
1±0.2Vrms
Test Method
2
3
4
5
See the previous pages
No defects or abnormality
See the previous pages
No defect or abnormality
Morn than 100000MΩ or 500
ΩF
(Whichever is smaller)
Within the specified tolerance
C＞30pF, Q≥1000
C≤30pF, Q≥400+20C(pF)
6
7
8
9
Temperature
Coefficient
Temperature coefficient: within
the specified tolerance.
Capacitance drift: within 0.3%
or 0.05pF
(Whichever is larger)
The temperature coefficient is measured with the capacitance
of step 3 as a reference. The temperature cycling sequential is
from step 1 through 5, The temperature coefficient shall be
within the specified tolerance for the temperature coefficient.
The temperature coefficient equal [(Ci-C
3
)/C
3
]/(Ti-T
3
).
The capacitance drift is calculated by dividing the differences
between the maximum and minimum measured values in the
step 1,3 and 5 by the capacitance value in step 3.
Step
1
2
3
4
5
Temperature
25±2℃
-55±3℃
25±2℃
125±3℃
25±2℃
10
Adhesive
Strength of
Termination
No removal of the terminations
or other defect shall occur.
Solder a capacitor to test jig (glass epoxy board) shown in
below fig using a eutectic solder. Then apply 10N force in
the direction of the arrow.
The soldering should be done either by hand iron or using the
reflow method and shall be conducted with care so that the
soldering is uniform and free of defects such as heat
