Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS "L", SnPb Termination, X7R Dielectric,
10 – 250 VDC (Commercial Grade)
Overview
KEMET Power Solutions (KPS) Commercial "L" with Tin/
Lead Termination stacked capacitors utilize a proprietary
lead-frame technology to vertically stack one or two
multilayer ceramic chip capacitors into a single compact
surface mount package. The attached lead-frame
mechanically isolates the capacitor's from the printed
circuit board, therefore offering advanced mechanical
and thermal stress performance. Isolation also addresses
concerns for audible, microphonic noise that may occur
when a bias voltage is applied. A two chip stack offers
up to double the capacitance in the same or smaller
design footprint when compared to traditional surface
mount MLCC devices. Providing up to 10 mm of board
flex capability, KEMET’s tin/lead electroplating process is
designed to meet a 5% minimum lead content and address
concerns for a more robust and reliable lead containing
termination system. As the bulk of the electronics industry
moves towards RoHS compliance, KEMET continues to
provide tin/lead terminated products for military, aerospace
and industrial applications and will ensure customers have a
stable and long-term source of supply. These devices provide
lower ESR, ESL and higher ripple current capability when
compared to other dielectric solutions.
Combined with the stability of an X7R dielectric, KEMET’s
KPS devices exhibit a predictable change in capacitance
with respect to time and voltage and boast a minimal change
in capacitance with reference to ambient temperature.
Capacitance change is limited to ±15% from −55°C to
+125°C.
Benefits
• Operating temperature range of −55°C to +125°C
• Reliable and robust termination system
• EIA 1210 and 2220 case sizes
• DC voltage ratings of 10 V, 16 V, 25 V, 50 V, 100 V and 250 V
• Capacitance offerings ranging from 0.1 up to 47 μF
Ordering Information
C
2220
C
106
M
5
R
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2
Failure Rate/
Design
1 = KPS Single Chip Stack
2 = KPS Double Chip Stack
L
Leadframe
Finish
2
L = SnPb
(5% Pb min.)
7186
Packaging/
Grade
(C-Spec)
See
"Packaging
C-Spec
Ordering
Options Table"
Case Size
Specification/
Capacitance Capacitance
Ceramic
(L" x W")
Series
Code (pF)
Tolerance
1
1210
2220
C = Standard
Two
Significant
Digits and
Number of
Zeroes
K = ±10%
M = ±20%
Rated
Voltage Dielectric
(VDC)
8 = 10
4 = 16
3 = 25
5 = 50
1 = 100
A = 250
R = X7R
Double chip stacks ("2" in the 13th character position of the ordering code) are only available in M (±20%) capacitance tolerance.
Single chip stacks ("1" in the 13th character position of the ordering code) are available in K (±10%) or M (±20%) tolerances.
2
Additional leadframe finish options may be available. Contact KEMET for details.
1
One world. One KEMET
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com
C1089_X7R_KPS_SnPb • 8/2/2019
1
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS "L", SnPb Termination, X7R Dielectric, 10 – 250VDC (Commercial Grade)
Packaging C-Spec Ordering Options Table
Packaging Type
1
7" Reel (Embossed Plastic Tape)/Unmarked
13" Reel (Embossed Plastic Tape)/Unmarked
1
Packaging/Grade
Ordering Code (C-Spec)
7186
7289
The terms "Marked" and "Unmarked" pertain to laser marking option of capacitors. All packaging options labeled as "Unmarked" will contain capacitors
that have not been laser marked. The option to laser mark is not available on these devices. For more information see "Capacitor Marking."
Benefits cont'd
• Available capacitance tolerances of ±10% and ±20%
• Higher capacitance in the same footprint
• Potential board space savings
• Advanced protection against thermal and mechanical stress
• Provides up to 10mm of board flex capability
• Reduces audible, microphonic noise
• Extremely low ESR and ESL
• SnPb plated termination finish (5% Pb minimum)
• Non-polar device, minimizing installation concerns
• Tantalum and electrolytic alternative
Applications
Typical applications include smoothing circuits, DC/DC converters, power supplies (input/output filters), noise reduction
(piezoelectric/mechanical), circuits with a direct battery or power source connection, critical and safety relevant circuits
without (integrated) current limitation, and any application that is subject to high levels of board flexure or temperature
cycling. Markets include industrial, aerospace, automotive and telecommunications.
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com
C1089_X7R_KPS_SnPb • 8/2/2019
2
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS "L", SnPb Termination, X7R Dielectric, 10 – 250VDC (Commercial Grade)
Qualification/Certification
Commercial grade products are subject to internal qualification. Details regarding test methods and conditions are
referenced in Table 4, Performance & Reliability.
Environmental Compliance
These devices do not meet RoHS criteria due to the concentration of Lead (Pb) in the termination finish.
Dimensions – Inches (Millimeters)
TOP VIEW
Single or Double Chip Stack
Double Chip Stack
PROFILE VIEW
Single Chip Stack
L
L
W
H
H
LW
LW
Number of
Chips
Single
EIA
SIZE CODE
1210
2220
1210
2220
METRIC
SIZE CODE
3225
5650
3225
5650
L
LENGTH
3.50 (0.138)
±0.30 (0.012)
6.00 (0.236)
±0.50 (0.020)
3.50 (0.138)
±0.30 (0.012)
6.00 (0.236)
±0.50 (0.020)
W
WIDTH
2.60 (0.102)
±0.30 (0.012)
5.00 (0.197)
±0.50 (0.020)
2.60 (0.102)
±0.30 (0.012)
5.00 (0.197)
±0.50 (0.020)
H
HEIGHT
3.35 (0.132)
±0.10 (0.004)
3.50 (0.138)
±0.30 (0.012)
6.15 (0.242)
±0.15 (0.006)
5.00 (0.197)
±0.50 (0.020)
LW
LEAD WIDTH
0.80 (0.032)
±0.15 (0.006)
1.60 (0.063)
±0.30 (0.012)
0.80 (0.031)
±0.15 (0.006)
1.60 (0.063)
±0.30 (0.012)
Mounting
Technique
Solder Reflow
Only
Double
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com
C1089_X7R_KPS_SnPb • 8/2/2019
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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS "L", SnPb Termination, X7R Dielectric, 10 – 250VDC (Commercial Grade)
Electrical Parameters/Characteristics
Item
Operating Temperature Range
Capacitance Change with Reference
to +25°C and 0 Vdc Applied (TCC)
1
Parameters/Characteristics
−55°C to +125°C
±15%
3.0%
250% of rated voltage
(5 ±1 seconds and charge/discharge not exceeding 50 mA)
5% (10 V), 3.5% (16 V and 25 V) and 2.5%(50 V to 250 V)
See Insulation Resistance Limit Table
(Rated voltage applied for 120 ±5 seconds at 25°C)
Aging Rate (Maximum % Capacitance Loss/Decade Hour)
2
Dielectric Withstanding Voltage (DWV)
3
Dissipation Factor (DF) Maximum Limit at 25°C
4
Insulation Resistance (IR) Minimum Limit at 25°C
Regarding Aging Rate: Capacitance measurements (including tolerance) are indexed to a referee time of 48 or 1,000 hours. Please refer to a part
number specific datasheet for referee time details.
2
DWV is the voltage a capacitor can withstand (survive) for a short period of time. It exceeds the nominal and continuous working voltage of the
capacitor.
3
Capacitance and dissipation factor (DF) measured under the following conditions:
1 kHz ±50 Hz and 1.0 ±0.2 V
rms
if capacitance ≤ 10 µF
120 Hz ±10 Hz and 0.5 ±0.1 V
rms
if capacitance > 10 µF
4
To obtain IR limit, divide MΩ - µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits.
Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 and Agilent E4980 have a feature known
as Automatic Level Control (ALC). The ALC feature should be switched to "ON."
1
Post Environmental Limits
High Temperature Life, Biased Humidity, Moisture Resistance
Dielectric
Rated DC
Voltage
> 25
X7R
16/25
< 16
All
Capacitance
Value
Dissipation Factor
(Maximum %)
3.0
5.0
7.5
±20%
10% of Initial
Limit
Capacitance
Shift
Insulation
Resistance
Insulation Resistance Limit Table
EIA Case Size
1210
2220
1,000 Megohm
Microfarads or 100 GΩ
< 0.39 µF
< 10 µF
500 Megohm
Microfarads or 10 GΩ
≥ 0.39 µF
≥ 10 µF
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com
C1089_X7R_KPS_SnPb • 8/2/2019
4
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
KPS "L", SnPb Termination, X7R Dielectric, 10 – 250VDC (Commercial Grade)
Electrical Characteristics
Z and
C1210C475M5R1C Z and ESR
ESR C1210C475M5R1L
10
3
Z and ESR C2220C225MAR2L
10
ESR
Z
4
ESR
10
3
Z
10
2
10
2
Magnitude Ohms
Magnitude Ohms
10
1
1
10
10
0
10
0
10
-1
10
-1
10
-2
10
-2
10
-3
10
10
0
-3
10
2
10
4
10
6
10
8
10
10
10
0
10
2
10
4
10
6
10
8
10
10
Frequency (Hz)
Frequency (Hz)
Z and ESR C2220C476M3R2L
10
4
ESR – 1210, .22 µF, 50 V X7R
ESR
Z
10
ESR vs. Frequency
C1210C224K5R2C (2 Chip Stack)
C1210C224K5R1C (1 Chip Stack)
10
2
Magnitude Ohms
10
-2
10
-4
10
-6
10
0
10
2
10
4
10
6
10
8
10
10
ESR (Ohms)
10
0
1
0.1
Frequency (Hz)
0.01
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
Frequency (Hz)
Impedance – 1210, .22 µF, 50 V X7R
1000
100
Impedance vs. Frequency
C1210C224K5R2C (2 Chip Stack)
C1210C224K5R1C (1 Chip Stack)
Impedance (Ohms)
10
1
0.1
0.01
1.E+03
1.E+04
1.E+05
1.E+06
Frequency (Hz)
1.E+07
1.E+08
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com
C1089_X7R_KPS_SnPb • 8/2/2019
5
嵌入式系统
