C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Mixed Signal ISP Flash MCU Family
Analog Peripherals
-
10 or 12-bit SAR ADC
•
± 1 LSB INL
•
Programmable Throughput up to 100 ksps
•
Up to 8 External Inputs; Programmable as Single-
•
•
•
•
•
•
•
Ended or Differential
Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
Data-Dependent Windowed Interrupt Generator
Built-in Temperature Sensor
Programmable Throughput up to 500 ksps
8 External Inputs (Single-Ended or Differential)
Programmable Amplifier Gain: 4, 2, 1, 0.5
Can Synchronize Outputs to Timers for Jitter-Free
Waveform Generation
High Speed 8051
µC
Core
-
Pipelined Instruction Architecture; Executes 70% of
-
-
Instruction Set in 1 or 2 System Clocks
100 MIPS or 50 MIPS Throughput with On-chip PLL
2-cycle 16 x 16 MAC Engine (C8051F120/1/2/3 and
C8051F130/1/2/3 Only)
-
8-bit SAR ADC (‘F12x Only)
Memory
-
8448 Bytes Internal Data RAM (8k + 256)
-
128k or 64k Bytes Banked FLASH; In-System pro-
-
grammable in 1024-byte Sectors
External 64k Byte Data Memory Interface (program-
mable multiplexed or non-multiplexed modes)
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Two 12-bit DACs (‘F12x Only)
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Two Analog Comparators
-
Voltage Reference
-
VDD Monitor/Brown-Out Detector
On-Chip JTAG Debug & Boundary Scan
-
On-chip debug circuitry facilitates full-speed, non-
-
-
intrusive in-circuit/in-system debugging
Provides breakpoints, single-stepping, watchpoints,
stack monitor; inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
IEEE1149.1 compliant boundary scan
Complete development kit
Digital Peripherals
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8 Byte-Wide Port I/O (100TQFP); 5V tolerant
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4 Byte-Wide Port I/O (64TQFP); 5V tolerant
-
Hardware SMBus™ (I
2
C™ Compatible), SPI™, and
-
Two UART Serial Ports Available Concurrently
Programmable 16-bit Counter/Timer Array with
6 Capture/Compare Modules
5 General Purpose 16-bit Counter/Timers
Dedicated Watchdog Timer; Bi-directional Reset Pin
-
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100-Pin TQFP or 64-Pin TQFP Packaging
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Temperature Range: -40°C to +85°C
-
-
Clock Sources
-
Internal Precision Oscillator: 24.5 MHz
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Flexible PLL technology
-
External Oscillator: Crystal, RC, C, or Clock
Voltage Supples
-
Range: 2.7-3.6V (50 MIPS) 3.0-3.6V (100 MIPS)
-
Power Saving Sleep and Shutdown Modes
ANALOG PERIPHERALS
VREF
DIGITAL I/O
UART0
UART1
SMBus
SPI Bus
PCA
Timer 0
Timer 1
Timer 2
CROSSBAR
External Memory Interface
PGA
10/12-bit
100ksps
ADC
TEMP
SENSOR
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
64 pin
100 pin
AMUX
+
-
+
-
VOLTAGE
COMPARATORS
PGA
8-bit
500ksps
ADC
AMUX
12-Bit
DAC
12-Bit
DAC
Timer 3
Timer 4
C8051F12x Only
HIGH-SPEED CONTROLLER CORE
8051 CPU
128/64 kB 8448 B
16 x 16 MAC
(50 or 100MIPS)
ISP FLASH SRAM ('F120/1/2/3, 'F13x)
20
DEBUG
CLOCK / PLL
JTAG
INTERRUPTS
CIRCUITRY
CIRCUIT
Rev. 1.3 8/04
Copyright © 2004 by Silicon Laboratories
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
2
Rev. 1.3
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table of Contents
1. System Overview.................................................................................................... 19
1.1. CIP-51™ Microcontroller Core.......................................................................... 27
1.1.1. Fully 8051 Compatible.............................................................................. 27
1.1.2. Improved Throughput ............................................................................... 27
1.1.3. Additional Features .................................................................................. 28
1.2. On-Chip Memory............................................................................................... 29
1.3. JTAG Debug and Boundary Scan..................................................................... 30
1.4. 16 x 16 MAC (Multiply and Accumulate) Engine............................................... 31
1.5. Programmable Digital I/O and Crossbar ........................................................... 32
1.6. Programmable Counter Array ........................................................................... 33
1.7. Serial Ports ....................................................................................................... 34
1.8. 12 or 10-Bit Analog to Digital Converter ........................................................... 35
1.9. 8-Bit Analog to Digital Converter....................................................................... 36
1.10.12-bit Digital to Analog Converters................................................................... 37
1.11.Analog Comparators......................................................................................... 38
2. Absolute Maximum Ratings .................................................................................. 39
3. Global DC Electrical Characteristics .................................................................... 40
4. Pinout and Package Definitions............................................................................ 42
5. ADC0 (12-Bit ADC, C8051F120/1/4/5 Only)........................................................... 57
5.1. Analog Multiplexer and PGA............................................................................. 57
5.2. ADC Modes of Operation.................................................................................. 59
5.2.1. Starting a Conversion............................................................................... 59
5.2.2. Tracking Modes........................................................................................ 60
5.2.3. Settling Time Requirements ..................................................................... 61
5.3. ADC0 Programmable Window Detector ........................................................... 68
6. ADC0 (10-Bit ADC, C8051F122/3/6/7 and C8051F13x Only)................................ 75
6.1. Analog Multiplexer and PGA............................................................................. 75
6.2. ADC Modes of Operation.................................................................................. 77
6.2.1. Starting a Conversion............................................................................... 77
6.2.2. Tracking Modes........................................................................................ 78
6.2.3. Settling Time Requirements ..................................................................... 79
6.3. ADC0 Programmable Window Detector ........................................................... 86
7. ADC2 (8-Bit ADC, C8051F12x Only)...................................................................... 93
7.1. Analog Multiplexer and PGA............................................................................. 93
7.2. ADC2 Modes of Operation................................................................................ 94
7.2.1. Starting a Conversion............................................................................... 94
7.2.2. Tracking Modes........................................................................................ 94
7.2.3. Settling Time Requirements ..................................................................... 96
7.3. ADC2 Programmable Window Detector ......................................................... 102
7.3.1. Window Detector In Single-Ended Mode ............................................... 102
7.3.2. Window Detector In Differential Mode.................................................... 103
8. DACs, 12-Bit Voltage Mode (C8051F12x Only) .................................................. 107
Rev. 1.3
3
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
8.1. DAC Output Scheduling.................................................................................. 107
8.1.1. Update Output On-Demand ................................................................... 107
8.1.2. Update Output Based on Timer Overflow .............................................. 108
8.2. DAC Output Scaling/Justification .................................................................... 108
9. Voltage Reference ................................................................................................ 115
9.1. Reference Configuration on the C8051F120/2/4/6 ......................................... 115
9.2. Reference Configuration on the C8051F121/3/5/7 ......................................... 117
9.3. Reference Configuration on the C8051F130/1/2/3 ......................................... 119
10. Comparators ......................................................................................................... 121
11. CIP-51 Microcontroller ......................................................................................... 129
11.1.Instruction Set................................................................................................. 131
11.1.1.Instruction and CPU Timing ................................................................... 131
11.1.2.MOVX Instruction and Program Memory ............................................... 131
11.2.Memory Organization ..................................................................................... 136
11.2.1.Program Memory ................................................................................... 136
11.2.2.Data Memory.......................................................................................... 138
11.2.3.General Purpose Registers.................................................................... 138
11.2.4.Bit Addressable Locations...................................................................... 138
11.2.5.Stack ..................................................................................................... 138
11.2.6.Special Function Registers .................................................................... 139
11.2.6.1.SFR Paging ................................................................................... 139
11.2.6.2.Interrupts and SFR Paging ............................................................ 139
11.2.6.3.SFR Page Stack Example ............................................................. 141
11.2.7.Register Descriptions ............................................................................. 155
11.3.Interrupt Handler............................................................................................. 158
11.3.1.MCU Interrupt Sources and Vectors ...................................................... 158
11.3.2.External Interrupts.................................................................................. 158
11.3.3.Interrupt Priorities................................................................................... 160
11.3.4.Interrupt Latency .................................................................................... 160
11.3.5.Interrupt Register Descriptions............................................................... 161
11.4.Power Management Modes............................................................................ 167
11.4.1.Idle Mode ............................................................................................... 167
11.4.2.Stop Mode.............................................................................................. 168
12. Multiply And Accumulate (MAC0) ....................................................................... 169
12.1.Special Function Registers............................................................................. 169
12.2.Integer and Fractional Math............................................................................ 170
12.3.Operating in Multiply and Accumulate Mode .................................................. 171
12.4.Operating in Multiply Only Mode .................................................................... 171
12.5.Accumulator Shift Operations......................................................................... 171
12.6.Rounding and Saturation................................................................................ 172
12.7.Usage Examples ............................................................................................ 172
13. Reset Sources....................................................................................................... 181
13.1.Power-on Reset.............................................................................................. 182
13.2.Power-fail Reset ............................................................................................. 182
13.3.External Reset ................................................................................................ 183
4
Rev. 1.3
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
13.4.Missing Clock Detector Reset ........................................................................ 183
13.5.Comparator0 Reset ........................................................................................ 183
13.6.External CNVSTR0 Pin Reset ........................................................................ 183
13.7.Watchdog Timer Reset................................................................................... 183
13.7.1.Enable/Reset WDT ................................................................................ 184
13.7.2.Disable WDT .......................................................................................... 184
13.7.3.Disable WDT Lockout ............................................................................ 184
13.7.4.Setting WDT Interval .............................................................................. 184
14. Oscillators ............................................................................................................. 189
14.1.Internal Calibrated Oscillator .......................................................................... 189
14.2.External Oscillator Drive Circuit...................................................................... 191
14.3.System Clock Selection.................................................................................. 191
14.4.External Crystal Example ............................................................................... 194
14.5.External RC Example ..................................................................................... 194
14.6.External Capacitor Example ........................................................................... 194
14.7.Phase-Locked Loop (PLL).............................................................................. 195
14.7.1.PLL Input Clock and Pre-divider ............................................................ 195
14.7.2.PLL Multiplication and Output Clock ...................................................... 195
14.7.3.Powering on and Initializing the PLL ...................................................... 196
15. FLASH Memory..................................................................................................... 201
15.1.Programming The Flash Memory ................................................................... 201
15.1.1.Non-volatile Data Storage ...................................................................... 202
15.1.2.Erasing FLASH Pages From Software................................................... 203
15.1.3.Writing FLASH Memory From Software................................................. 204
15.2.Security Options ............................................................................................. 205
15.2.1.Summary of Flash Security Options....................................................... 209
16. Branch Target Cache ........................................................................................... 213
16.1.Cache and Prefetch Operation ....................................................................... 213
16.2.Cache and Prefetch Optimization................................................................... 214
17. External Data Memory Interface and On-Chip XRAM........................................ 221
17.1.Accessing XRAM............................................................................................ 221
17.1.1.16-Bit MOVX Example ........................................................................... 221
17.1.2.8-Bit MOVX Example ............................................................................. 221
17.2.Configuring the External Memory Interface .................................................... 221
17.3.Port Selection and Configuration.................................................................... 222
17.4.Multiplexed and Non-multiplexed Selection.................................................... 225
17.4.1.Multiplexed Configuration....................................................................... 225
17.4.2.Non-multiplexed Configuration............................................................... 226
17.5.Memory Mode Selection................................................................................. 227
17.5.1.Internal XRAM Only ............................................................................... 227
17.5.2.Split Mode without Bank Select.............................................................. 227
17.5.3.Split Mode with Bank Select................................................................... 228
17.5.4.External Only.......................................................................................... 228
17.6.EMIF Timing ................................................................................................... 229
17.6.1.Non-multiplexed Mode ........................................................................... 230
Rev. 1.3
5
