C8051F120/1/2/3/4/5/6/7
8K ISP FLASH MCU Family
Analog Peripherals
-
10 or 12-bit SAR ADC
•
•
•
•
•
•
High Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
-
-
instruction set in 1 or 2 system clocks
100 MIPS or 50 MIPS throughput with on-chip PLL
2-cycle 16 x 16 MAC engine (C8051F120/1/2/3 and
C8051F130/1/2/3 only)
± 1 LSB INL
Programmable throughput up to 100 ksps
Up to 8 external inputs; programmable as single-
ended or differential
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor
Programmable throughput up to 500 ksps
8 external inputs (single-ended or differential)
Programmable amplifier gain: 4, 2, 1, 0.5
Can synchronize outputs to timers for jitter-free wave-
form generation
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8-bit SAR ADC (‘F12x Only)
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•
•
Memory
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8448 bytes internal data RAM (8 k + 256)
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128 or 64 kB Banked Flash; in-system programma-
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ble in 1024-byte sectors
External 64 kB data memory interface (programma-
ble multiplexed or non-multiplexed modes)
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Two 12-bit DACs (‘F12x Only)
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Two Analog Comparators
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Voltage Reference
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V
DD
Monitor/Brown-Out Detector
On-Chip JTAG Debug & Boundary Scan
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On-chip debug circuitry facilitates full-speed, non-
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intrusive in-circuit/in-system debugging
Provides breakpoints, single-stepping, watchpoints,
stack monitor; inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
IEEE1149.1 compliant boundary scan
Complete development kit
Digital Peripherals
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8 byte-wide port I/O (100TQFP); 5 V tolerant
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4 Byte-wide port I/O (64TQFP); 5 V tolerant
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Hardware SMBus™ (I2C™ Compatible), SPI™, and
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two UART serial ports available concurrently
Programmable 16-bit counter/timer array with
6 capture/compare modules
5 general purpose 16-bit counter/timers
Dedicated watchdog timer; bi-directional reset pin
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100-Pin TQFP or 64-Pin TQFP Packaging
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Temperature Range: –40 to +85 °C
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RoHS Available
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Clock Sources
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Internal precision oscillator: 24.5 MHz
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Flexible PLL technology
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External Oscillator: Crystal, RC, C, or clock
Voltage Supples
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Range: 2.7–3.6 V (50 MIPS) 3.0–3.6 V (100 MIPS)
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Power saving sleep and shutdown modes
ANALOG PERIPHERALS
VREF
DIGITAL I/O
UART0
UART1
SMBus
SPI Bus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
CROSSBAR
External Memory Interface
PGA
10/12-bit
100ksps
ADC
TEMP
SENSOR
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
64 pin
100 pin
AMUX
+
-
+
-
VOLTAGE
COMPARATORS
PGA
8-bit
500ksps
ADC
AMUX
12-Bit
DAC
12-Bit
DAC
C8051F12x Only
HIGH-SPEED CONTROLLER CORE
8051 CPU
128/64 kB 8448 B
16 x 16 MAC
(50 or 100MIPS)
ISP FLASH SRAM ('F120/1/2/3, 'F13x)
20
DEBUG
CLOCK / PLL
JTAG
INTERRUPTS
CIRCUITRY
CIRCUIT
Rev. 1.4 12/03
Copyright © 2003 by Silicon Laboratories
C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
N
OTES
:
2
Rev. 1.4
C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
Table of Contents
1. System Overview.................................................................................................... 19
1.1. CIP-51™ Microcontroller Core.......................................................................... 27
1.1.1. Fully 8051 Compatible.............................................................................. 27
1.1.2. Improved Throughput ............................................................................... 27
1.1.3. Additional Features .................................................................................. 28
1.2. On-Chip Memory............................................................................................... 29
1.3. JTAG Debug and Boundary Scan..................................................................... 30
1.4. 16 x 16 MAC (Multiply and Accumulate) Engine............................................... 31
1.5. Programmable Digital I/O and Crossbar ........................................................... 32
1.6. Programmable Counter Array ........................................................................... 33
1.7. Serial Ports ....................................................................................................... 33
1.8. 12 or 10-Bit Analog to Digital Converter ........................................................... 34
1.9. 8-Bit Analog to Digital Converter....................................................................... 35
1.10.12-bit Digital to Analog Converters................................................................... 36
1.11.Analog Comparators......................................................................................... 37
2. Absolute Maximum Ratings .................................................................................. 38
3. Global DC Electrical Characteristics .................................................................... 39
4. Pinout and Package Definitions............................................................................ 41
5. ADC0 (12-Bit ADC, C8051F120/1/4/5 Only)........................................................... 55
5.1. Analog Multiplexer and PGA............................................................................. 55
5.2. ADC Modes of Operation.................................................................................. 57
5.2.1. Starting a Conversion............................................................................... 57
5.2.2. Tracking Modes........................................................................................ 58
5.2.3. Settling Time Requirements ..................................................................... 59
5.3. ADC0 Programmable Window Detector ........................................................... 66
6. ADC0 (10-Bit ADC, C8051F122/3/6/7 and C8051F13x Only)................................ 73
6.1. Analog Multiplexer and PGA............................................................................. 73
6.2. ADC Modes of Operation.................................................................................. 75
6.2.1. Starting a Conversion............................................................................... 75
6.2.2. Tracking Modes........................................................................................ 76
6.2.3. Settling Time Requirements ..................................................................... 77
6.3. ADC0 Programmable Window Detector ........................................................... 84
7. ADC2 (8-Bit ADC, C8051F12x Only)...................................................................... 91
7.1. Analog Multiplexer and PGA............................................................................. 91
7.2. ADC2 Modes of Operation................................................................................ 92
7.2.1. Starting a Conversion............................................................................... 92
7.2.2. Tracking Modes........................................................................................ 92
7.2.3. Settling Time Requirements ..................................................................... 94
7.3. ADC2 Programmable Window Detector ......................................................... 100
7.3.1. Window Detector In Single-Ended Mode ............................................... 100
7.3.2. Window Detector In Differential Mode.................................................... 101
Rev. 1.4
3
C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
8. DACs, 12-Bit Voltage Mode (C8051F12x Only) .................................................. 105
8.1. DAC Output Scheduling.................................................................................. 105
8.1.1. Update Output On-Demand ................................................................... 106
8.1.2. Update Output Based on Timer Overflow .............................................. 106
8.2. DAC Output Scaling/Justification .................................................................... 106
9. Voltage Reference ................................................................................................ 113
9.1. Reference Configuration on the C8051F120/2/4/6 ......................................... 113
9.2. Reference Configuration on the C8051F121/3/5/7 ......................................... 115
9.3. Reference Configuration on the C8051F130/1/2/3 ......................................... 117
10. Comparators ......................................................................................................... 119
11. CIP-51 Microcontroller ......................................................................................... 127
11.1.Instruction Set................................................................................................. 129
11.1.1.Instruction and CPU Timing ................................................................... 129
11.1.2.MOVX Instruction and Program Memory ............................................... 129
11.2.Memory Organization ..................................................................................... 133
11.2.1.Program Memory ................................................................................... 133
11.2.2.Data Memory.......................................................................................... 135
11.2.3.General Purpose Registers.................................................................... 135
11.2.4.Bit Addressable Locations...................................................................... 135
11.2.5.Stack ..................................................................................................... 135
11.2.6.Special Function Registers .................................................................... 136
11.2.7.Register Descriptions ............................................................................. 151
11.3.Interrupt Handler............................................................................................. 154
11.3.1.MCU Interrupt Sources and Vectors ...................................................... 154
11.3.2.External Interrupts.................................................................................. 155
11.3.3.Interrupt Priorities................................................................................... 156
11.3.4.Interrupt Latency .................................................................................... 156
11.3.5.Interrupt Register Descriptions............................................................... 157
11.4.Power Management Modes............................................................................ 163
11.4.1.Idle Mode ............................................................................................... 163
11.4.2.Stop Mode.............................................................................................. 164
12. Multiply And Accumulate (MAC0) ....................................................................... 165
12.1.Special Function Registers............................................................................. 165
12.2.Integer and Fractional Math............................................................................ 166
12.3.Operating in Multiply and Accumulate Mode .................................................. 167
12.4.Operating in Multiply Only Mode .................................................................... 167
12.5.Accumulator Shift Operations......................................................................... 167
12.6.Rounding and Saturation................................................................................ 168
12.7.Usage Examples ............................................................................................ 168
12.7.1.Multiply and Accumulate Example ......................................................... 168
12.7.2.Multiply Only Example............................................................................ 169
12.7.3.MAC0 Accumulator Shift Example ......................................................... 169
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Rev. 1.4
C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3
13. Reset Sources....................................................................................................... 177
13.1.Power-on Reset.............................................................................................. 178
13.2.Power-fail Reset ............................................................................................. 178
13.3.External Reset ................................................................................................ 179
13.4.Missing Clock Detector Reset ........................................................................ 179
13.5.Comparator0 Reset ........................................................................................ 179
13.6.External CNVSTR0 Pin Reset ........................................................................ 179
13.7.Watchdog Timer Reset................................................................................... 179
13.7.1.Enable/Reset WDT ................................................................................ 180
13.7.2.Disable WDT .......................................................................................... 180
13.7.3.Disable WDT Lockout ............................................................................ 180
13.7.4.Setting WDT Interval .............................................................................. 180
14. Oscillators ............................................................................................................. 185
14.1.Internal Calibrated Oscillator .......................................................................... 185
14.2.External Oscillator Drive Circuit...................................................................... 187
14.3.System Clock Selection.................................................................................. 187
14.4.External Crystal Example ............................................................................... 190
14.5.External RC Example ..................................................................................... 190
14.6.External Capacitor Example ........................................................................... 190
14.7.Phase-Locked Loop (PLL).............................................................................. 191
14.7.1.PLL Input Clock and Pre-divider ............................................................ 191
14.7.2.PLL Multiplication and Output Clock ...................................................... 191
14.7.3.Powering on and Initializing the PLL ...................................................... 192
15. Flash Memory ....................................................................................................... 199
15.1.Programming the Flash Memory .................................................................... 199
15.1.1.Non-volatile Data Storage ...................................................................... 200
15.1.2.Erasing Flash Pages From Software ..................................................... 201
15.1.3.Writing Flash Memory From Software.................................................... 202
15.2.Security Options ............................................................................................. 203
15.2.1.Summary of Flash Security Options....................................................... 207
16. Branch Target Cache ........................................................................................... 211
16.1.Cache and Prefetch Operation ....................................................................... 211
16.2.Cache and Prefetch Optimization................................................................... 212
17. External Data Memory Interface and On-Chip XRAM........................................ 219
17.1.Accessing XRAM............................................................................................ 219
17.1.1.16-Bit MOVX Example ........................................................................... 219
17.1.2.8-Bit MOVX Example ............................................................................. 219
17.2.Configuring the External Memory Interface .................................................... 219
17.3.Port Selection and Configuration.................................................................... 220
17.4.Multiplexed and Non-multiplexed Selection.................................................... 222
17.4.1.Multiplexed Configuration....................................................................... 222
17.4.2.Non-multiplexed Configuration............................................................... 223
17.5.Memory Mode Selection................................................................................. 224
17.5.1.Internal XRAM Only ............................................................................... 224
17.5.2.Split Mode without Bank Select.............................................................. 224
Rev. 1.4
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