C8051F320/1
Full Speed USB, 16 k ISP FLASH MCU Family
Analog Peripherals
-
10-Bit ADC
•
•
•
•
•
High Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
-
-
Memory
-
2304 bytes internal RAM (1k + 256 + 1k USB FIFO)
-
16 kB Flash; In-system programmable in 512-byte
sectors
instructions in 1 or 2 system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
Up to 200 ksps
Up to 17 or 13 external single-ended or differential
inputs
VREF from external pin, internal reference, or VDD
Built-in temperature sensor
External conversion start input
-
Two Comparators
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Internal Voltage Reference
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POR/Brown-Out Detector
USB Function Controller
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USB specification 2.0 compliant
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Full speed (12 Mbps) or low speed (1.5 Mbps)
-
operation
Integrated clock recovery; no external crystal
required for full speed or low speed
Supports eight flexible endpoints
1 kB USB buffer memory
Integrated transceiver; no external resistors required
Digital Peripherals
-
25/21 Port I/O; All 5 V tolerant with high sink current
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Hardware enhanced SPI™, enhanced UART, and
-
-
-
SMBus™ serial ports
Four general purpose 16-bit counter/timers
16-bit programmable counter array (PCA) with five
capture/compare modules
Real time clock mode using external clock source
and PCA or timer
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-
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On-Chip Debug
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On-chip debug circuitry facilitates full speed,
-
-
Clock Sources
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Internal Oscillator: 0.25% accuracy with clock
-
-
recovery enabled. Supports all USB and UART
modes
External oscillator: Crystal, RC, C, or Clock
(1 or 2 pin modes)
Can switch between clock sources on-the-fly;
useful in power saving strategies
non-intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Voltage Regulator Input: 4.0 to 5.25 V
RoHS Compliant Packages
-
32-pin LQFP (C8051F320)
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28-pin QFN (C8051F321)
Temperature Range: –40 to +85 °C
CROSSBAR
ANALOG
PERIPHERALS
A
M
U
X
DIGITAL I/O
UART
SPI
SMBus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Port 0
Port 1
Port 2
Port 3
10-bit
200 ksps
ADC
+
-
+
-
TEMP
SENSOR
VREF
VREG
PRECISION INTERNAL
OSCILLATOR
USB Controller /
Transceiver
HIGH-SPEED CONTROLLER CORE
16 kB
ISP FLASH
16
INTERRUPTS
8051 CPU
(25MIPS)
DEBUG
CIRCUITRY
2304 B
SRAM
POR
WDT
Rev. 1.4 8/09
Copyright © 2009 by Silicon Laboratories
C8051F32x
C8051F320/1
2
Rev. 1.4
C8051F320/1
Table of Contents
1. System Overview.................................................................................................... 15
1.1. CIP-51™ Microcontroller Core.......................................................................... 18
1.1.1. Fully 8051 Compatible.............................................................................. 18
1.1.2. Improved Throughput ............................................................................... 18
1.1.3. Additional Features .................................................................................. 18
1.2. On-Chip Memory............................................................................................... 19
1.3. Universal Serial Bus Controller ......................................................................... 20
1.4. Voltage Regulator ............................................................................................. 21
1.5. On-Chip Debug Circuitry................................................................................... 21
1.6. Programmable Digital I/O and Crossbar ........................................................... 22
1.7. Serial Ports ....................................................................................................... 23
1.8. Programmable Counter Array ........................................................................... 23
1.9. 10-Bit Analog to Digital Converter..................................................................... 24
1.10.Comparators..................................................................................................... 25
2. Absolute Maximum Ratings .................................................................................. 27
3. Global Electrical Characteristics .......................................................................... 28
4. Pinout and Package Definitions............................................................................ 30
5. 10-Bit ADC (ADC0).................................................................................................. 39
5.1. Analog Multiplexer ............................................................................................ 40
5.2. Temperature Sensor ......................................................................................... 41
5.3. Modes of Operation .......................................................................................... 43
5.3.1. Starting a Conversion............................................................................... 43
5.3.2. Tracking Modes........................................................................................ 44
5.3.3. Settling Time Requirements ..................................................................... 45
5.4. Programmable Window Detector ...................................................................... 50
5.4.1. Window Detector In Single-Ended Mode ................................................. 52
5.4.2. Window Detector In Differential Mode...................................................... 53
6. Voltage Reference .................................................................................................. 55
7. Comparators ......................................................................................................... 57
8. Voltage Regulator (REG0)...................................................................................... 67
8.1. Regulator Mode Selection................................................................................. 67
8.2. VBUS Detection ................................................................................................ 67
9. CIP-51 Microcontroller .......................................................................................... 71
9.1. Instruction Set ................................................................................................... 72
9.1.1. Instruction and CPU Timing ..................................................................... 72
9.1.2. MOVX Instruction and Program Memory ................................................. 73
9.2. Memory Organization........................................................................................ 77
9.2.1. Program Memory...................................................................................... 77
9.2.2. Data Memory............................................................................................ 78
9.2.3. General Purpose Registers ...................................................................... 78
9.2.4. Bit Addressable Locations........................................................................ 78
9.2.5. Stack ....................................................................................................... 78
9.2.6. Special Function Registers....................................................................... 79
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9.2.7. Register Descriptions ............................................................................... 83
9.3. Interrupt Handler ............................................................................................... 87
9.3.1. MCU Interrupt Sources and Vectors ........................................................ 87
9.3.2. External Interrupts .................................................................................... 88
9.3.3. Interrupt Priorities ..................................................................................... 88
9.3.4. Interrupt Latency ...................................................................................... 89
9.3.5. Interrupt Register Descriptions................................................................. 90
9.4. Power Management Modes .............................................................................. 97
9.4.1. Idle Mode.................................................................................................. 97
9.4.2. Stop Mode ................................................................................................ 97
10. Reset Sources ....................................................................................................... 99
10.1.Power-On Reset ............................................................................................. 100
10.2.Power-Fail Reset / VDD Monitor .................................................................... 101
10.3.External Reset ................................................................................................ 102
10.4.Missing Clock Detector Reset ........................................................................ 102
10.5.Comparator0 Reset ........................................................................................ 102
10.6.PCA Watchdog Timer Reset .......................................................................... 102
10.7.Flash Error Reset ........................................................................................... 102
10.8.Software Reset ............................................................................................... 103
10.9.USB Reset...................................................................................................... 103
11. Flash Memory ..................................................................................................... 106
11.1.Programming The Flash Memory ................................................................... 106
11.1.1.Flash Lock and Key Functions ............................................................... 106
11.1.2.Flash Erase Procedure .......................................................................... 106
11.1.3.Flash Write Procedure ........................................................................... 107
11.2.Non-volatile Data Storage .............................................................................. 107
11.3.Security Options ............................................................................................. 108
11.4.Flash Write and Erase Guidelines .................................................................. 110
11.4.1.VDD Maintenance and the VDD Monitor ............................................... 110
11.4.2.16.4.2 PSWE Maintenance .................................................................... 111
11.4.3.System Clock ......................................................................................... 111
12. External RAM ...................................................................................................... 114
12.1.Accessing User XRAM ................................................................................... 114
12.2.Accessing USB FIFO Space .......................................................................... 114
13. Oscillators ............................................................................................................. 116
13.1.Programmable Internal Oscillator ................................................................... 116
13.1.1.Programming the Internal Oscillator on C8051F320/1 Devices ............. 117
13.1.2.Internal Oscillator Suspend Mode .......................................................... 118
13.2.External Oscillator Drive Circuit...................................................................... 119
13.2.1.Clocking Timers Directly Through the External Oscillator...................... 119
13.2.2.External Crystal Example....................................................................... 119
13.2.3.External RC Example............................................................................. 120
13.2.4.External Capacitor Example................................................................... 120
13.3.4x Clock Multiplier .......................................................................................... 122
13.4.System and USB Clock Selection .................................................................. 123
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13.4.1.System Clock Selection ......................................................................... 123
13.4.2.USB Clock Selection .............................................................................. 123
14. Port Input/Output ................................................................................................ 126
14.1.Priority Crossbar Decoder .............................................................................. 128
14.2.Port I/O Initialization ....................................................................................... 130
14.3.General Purpose Port I/O ............................................................................... 132
15. Universal Serial Bus Controller (USB)................................................................ 139
15.1.Endpoint Addressing ...................................................................................... 140
15.2.USB Transceiver ............................................................................................ 140
15.3.USB Register Access ..................................................................................... 142
15.4.USB Clock Configuration................................................................................ 146
15.5.FIFO Management ......................................................................................... 147
15.5.1.FIFO Split Mode ..................................................................................... 147
15.5.2.FIFO Double Buffering ........................................................................... 148
15.5.3.FIFO Access .......................................................................................... 148
15.6.Function Addressing....................................................................................... 149
15.7.Function Configuration and Control................................................................ 149
15.8.Interrupts ........................................................................................................ 152
15.9.The Serial Interface Engine ............................................................................ 157
15.10.Endpoint0 ..................................................................................................... 157
15.10.1.Endpoint0 SETUP Transactions .......................................................... 158
15.10.2.Endpoint0 IN Transactions................................................................... 158
15.10.3.Endpoint0 OUT Transactions............................................................... 159
15.11.Configuring Endpoints1–3 ............................................................................ 161
15.12.Controlling Endpoints1–3 IN......................................................................... 161
15.12.1.Endpoints1-3 IN Interrupt or Bulk Mode............................................... 161
15.12.2.Endpoints1-3 IN Isochronous Mode..................................................... 162
15.13.Controlling Endpoints1–3 OUT..................................................................... 164
15.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode........................................... 164
15.13.2.Endpoints1-3 OUT Isochronous Mode................................................. 165
16. SMBus ................................................................................................................... 169
16.1.Supporting Documents ................................................................................... 170
16.2.SMBus Configuration...................................................................................... 170
16.3.SMBus Operation ........................................................................................... 170
16.3.1.Arbitration............................................................................................... 171
16.3.2.Clock Low Extension.............................................................................. 171
16.3.3.SCL Low Timeout................................................................................... 171
16.3.4.SCL High (SMBus Free) Timeout .......................................................... 172
16.4.Using the SMBus............................................................................................ 172
16.4.1.SMBus Configuration Register............................................................... 173
16.4.2.SMB0CN Control Register ..................................................................... 176
16.4.3.Data Register ......................................................................................... 179
16.5.SMBus Transfer Modes.................................................................................. 180
16.5.1.Master Transmitter Mode ....................................................................... 180
16.5.2.Master Receiver Mode ........................................................................... 181
Rev. 1.4
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