C8051F58x/F59x
Mixed Signal ISP Flash MCU Family
Analog Peripherals
-
12-Bit ADC
•
•
•
•
•
Up to 200 ksps
Up to 32 external single-ended inputs
VREF from on-chip VREF, external pin or V
DD
Internal or external start of conversion source
Built-in temperature sensor
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current
Memory
-
8448 bytes internal data RAM (256 + 8192 XRAM)
-
128 or 96 kB Banked Flash; In-system programma-
-
ble in 512-byte Sectors
External 64 kB data memory interface programma-
ble for multiplexed or non-multiplexed mode
-
Three Comparators
•
•
•
Digital Peripherals
-
40, 33, or 25 Port I/O; All 5 V push-pull with high
-
-
-
-
-
sink current
CAN 2.0 Controller—no crystal required
LIN 2.1 Controller (Master and Slave capable); no
crystal required
Two Hardware enhanced UARTs, SMBus™, and
enhanced SPI™ serial ports
Six general purpose 16-bit counter/timers
Two 16-Bit programmable counter array (PCA)
peripherals with six capture/compare modules each
and enhanced PWM functionality
On-Chip Debug
-
On-chip debug circuitry facilitates full speed, non-
-
-
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Low cost, complete development kit
-
Supply Voltage 1.8 to 5.25 V
-
Typical operating current: 15 mA at 50 MHz;
Typical stop mode current: 230 µA
Clock Sources
-
Internal 24 MHz with ±0.5% accuracy for CAN and
-
-
master LIN operation.
External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
Can switch between clock sources on-the-fly;
useful in power saving modes
High-Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
-
-
Automotive Qualified
-
Temperature Range: –40 to +125 °C
instructions in 1 or 2 system clocks
Up to 50 MIPS throughput with 50 MHz clock
Expanded interrupt handler
Packages
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48-Pin QFP/QFN (C8051F580/1/4/5)
-
40-Pin QFN (C8051F588/9-F590/1)
-
32-Pin QFP/QFN (C8051F582/3/6/7)
ANALOG
PERIPHERALS
A
M
U
X
DIGITAL I/O
UART 0-1
SMBus
SPI
PCA x 2
Timers 0-5
CAN
LIN
Ports 0-4
Crossbar
External
Memory
Interface
12-bit
200 ksps
ADC
TEMP
SENSOR
VREG
Voltage
Comparators 0-2 VREF
24 MHz PRECISION
INTERNAL OSCILLATOR
2x Clock Multiplier
HIGH-SPEED CONTROLLER CORE
128 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(50 MIPS)
DEBUG
CIRCUITRY
8 kB XRAM
POR
WDT
Rev. 1.3 10/15
Copyright © 2015 by Silicon Laboratories
C8051F580/1/2/3/4/5/6/7/8/9-F590/1
C8051F58x/F59x
Table of Contents
1. System Overview ..................................................................................................... 18
2. Ordering Information ............................................................................................... 22
3. Pin Definitions.......................................................................................................... 24
4. Package Specifications ........................................................................................... 32
4.1. QFP-48 Package Specifications........................................................................ 32
4.2. QFN-48 Package Specifications........................................................................ 34
4.3. QFN-40 Package Specifications........................................................................ 36
4.4. QFP-32 Package Specifications........................................................................ 38
4.5. QFN-32 Package Specifications........................................................................ 40
5. Electrical Characteristics ........................................................................................ 42
5.1. Absolute Maximum Specifications..................................................................... 42
5.2. Electrical Characteristics ................................................................................... 43
6. 12-Bit ADC (ADC0) ................................................................................................... 54
6.1. Modes of Operation ........................................................................................... 55
6.1.1. Starting a Conversion................................................................................ 55
6.1.2. Tracking Modes......................................................................................... 55
6.1.3. Timing ....................................................................................................... 56
6.1.4. Burst Mode................................................................................................ 57
6.2. Output Code Formatting .................................................................................... 59
6.2.1. Settling Time Requirements...................................................................... 59
6.3. Selectable Gain ................................................................................................. 60
6.3.1. Calculating the Gain Value........................................................................ 60
6.3.2. Setting the Gain Value .............................................................................. 62
6.4. Programmable Window Detector....................................................................... 68
6.4.1. Window Detector In Single-Ended Mode .................................................. 70
6.5. ADC0 Analog Multiplexer .................................................................................. 72
7. Temperature Sensor ................................................................................................ 74
8. Voltage Reference.................................................................................................... 75
9. Comparators............................................................................................................. 77
9.1. Comparator Multiplexer ..................................................................................... 85
10. Voltage Regulator (REG0) ..................................................................................... 89
11. CIP-51 Microcontroller........................................................................................... 91
11.1. Performance .................................................................................................... 91
11.2. Instruction Set.................................................................................................. 93
11.2.1. Instruction and CPU Timing .................................................................... 93
11.3. CIP-51 Register Descriptions .......................................................................... 97
11.4. Serial Number Special Function Registers (SFRs) ....................................... 101
12. Memory Organization .......................................................................................... 102
12.1. Program Memory........................................................................................... 102
12.1.1. MOVX Instruction and Program Memory .............................................. 104
12.2. Data Memory ................................................................................................. 104
12.2.1. Internal RAM ......................................................................................... 105
12.2.1.1. General Purpose Registers .......................................................... 105
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C8051F58x/F59x
12.2.1.2. Bit Addressable Locations ............................................................ 105
12.2.1.3. Stack .......................................................................................... 105
13. Special Function Registers................................................................................. 106
13.1. SFR Paging ................................................................................................... 106
13.2. Interrupts and SFR Paging ............................................................................ 106
13.3. SFR Page Stack Example ............................................................................. 107
14. Interrupts .............................................................................................................. 126
14.1. MCU Interrupt Sources and Vectors.............................................................. 126
14.1.1. Interrupt Priorities.................................................................................. 127
14.1.2. Interrupt Latency ................................................................................... 127
14.2. Interrupt Register Descriptions ...................................................................... 129
14.3. External Interrupts INT0 and INT1................................................................. 136
15. Flash Memory....................................................................................................... 138
15.1. Programming The Flash Memory .................................................................. 138
15.1.1. Flash Lock and Key Functions .............................................................. 138
15.1.2. Flash Erase Procedure ......................................................................... 138
15.1.3. Flash Write Procedure .......................................................................... 139
15.1.4. Flash Write Optimization ....................................................................... 139
15.2. Non-volatile Data Storage ............................................................................. 140
15.3. Security Options ............................................................................................ 140
15.4. Flash Write and Erase Guidelines ................................................................. 142
15.4.1. V
DD
Maintenance and the V
DD
monitor ................................................ 142
15.4.2. PSWE Maintenance .............................................................................. 142
15.4.3. System Clock ........................................................................................ 143
16. Power Management Modes................................................................................. 147
16.1. Idle Mode....................................................................................................... 147
16.2. Stop Mode ..................................................................................................... 148
16.3. Suspend Mode .............................................................................................. 148
17. Reset Sources ...................................................................................................... 150
17.1. Power-On Reset ............................................................................................ 151
17.2. Power-Fail Reset/VDD Monitor ..................................................................... 152
17.3. External Reset ............................................................................................... 153
17.4. Missing Clock Detector Reset ....................................................................... 153
17.5. Comparator0 Reset ....................................................................................... 154
17.6. PCA Watchdog Timer Reset ......................................................................... 154
17.7. Flash Error Reset .......................................................................................... 154
17.8. Software Reset .............................................................................................. 154
18. External Data Memory Interface and On-Chip XRAM ....................................... 156
18.1. Accessing XRAM........................................................................................... 156
18.1.1. 16-Bit MOVX Example .......................................................................... 156
18.1.2. 8-Bit MOVX Example ............................................................................ 156
18.2. Configuring the External Memory Interface ................................................... 157
18.3. Port Configuration.......................................................................................... 157
18.4. Multiplexed and Non-multiplexed Selection................................................... 162
18.4.1. Multiplexed Configuration...................................................................... 162
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C8051F58x/F59x
18.4.2. Non-multiplexed Configuration.............................................................. 163
18.5. Memory Mode Selection................................................................................ 164
18.5.1. Internal XRAM Only .............................................................................. 164
18.5.2. Split Mode without Bank Select............................................................. 164
18.5.3. Split Mode with Bank Select.................................................................. 165
18.5.4. External Only......................................................................................... 165
18.6. Timing .......................................................................................................... 165
18.6.1. Non-Multiplexed Mode .......................................................................... 167
18.6.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111............................. 167
18.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111 ....... 168
18.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 110 ....................... 169
18.6.2. Multiplexed Mode .................................................................................. 170
18.6.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011............................. 170
18.6.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011 ....... 171
18.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010 ....................... 172
19. Oscillators and Clock Selection ......................................................................... 174
19.1. System Clock Selection................................................................................. 174
19.2. Programmable Internal Oscillator .................................................................. 176
19.2.1. Internal Oscillator Suspend Mode ......................................................... 176
19.3. Clock Multiplier .............................................................................................. 179
19.4. External Oscillator Drive Circuit..................................................................... 181
19.4.1. External Crystal Example...................................................................... 183
19.4.2. External RC Example............................................................................ 184
19.4.3. External Capacitor Example.................................................................. 184
20. Port Input/Output ................................................................................................. 186
20.1. Port I/O Modes of Operation.......................................................................... 188
20.1.1. Port Pins Configured for Analog I/O...................................................... 188
20.1.2. Port Pins Configured For Digital I/O...................................................... 188
20.1.3. Interfacing Port I/O in a Multi-Voltage System ...................................... 189
20.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 189
20.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 189
20.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 189
20.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 190
20.3. Priority Crossbar Decoder ............................................................................. 190
20.4. Port I/O Initialization ...................................................................................... 193
20.5. Port Match ..................................................................................................... 198
20.6. Special Function Registers for Accessing and Configuring Port I/O ............. 202
21. Local Interconnect Network (LIN0)..................................................................... 212
21.1. Software Interface with the LIN Controller..................................................... 213
21.2. LIN Interface Setup and Operation................................................................ 213
21.2.1. Mode Definition ..................................................................................... 213
21.2.2. Baud Rate Options: Manual or Autobaud ............................................. 213
21.2.3. Baud Rate Calculations: Manual Mode................................................. 213
21.2.4. Baud Rate Calculations—Automatic Mode ........................................... 215
21.3. LIN Master Mode Operation .......................................................................... 216
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C8051F58x/F59x
21.4. LIN Slave Mode Operation ............................................................................ 217
21.5. Sleep Mode and Wake-Up ............................................................................ 218
21.6. Error Detection and Handling ........................................................................ 218
21.7. LIN Registers................................................................................................. 219
21.7.1. LIN Direct Access SFR Registers Definitions ....................................... 219
21.7.2. LIN Indirect Access SFR Registers Definitions ..................................... 221
22. Controller Area Network (CAN0) ........................................................................ 229
22.1. Bosch CAN Controller Operation................................................................... 230
22.1.1. CAN Controller Timing .......................................................................... 230
22.1.2. CAN Register Access............................................................................ 231
22.1.3. Example Timing Calculation for 1 Mbit/Sec Communication ................ 231
22.2. CAN Registers............................................................................................... 233
22.2.1. CAN Controller Protocol Registers........................................................ 233
22.2.2. Message Object Interface Registers ..................................................... 233
22.2.3. Message Handler Registers.................................................................. 233
22.2.4. CAN Register Assignment .................................................................... 234
23. SMBus................................................................................................................... 237
23.1. Supporting Documents .................................................................................. 238
23.2. SMBus Configuration..................................................................................... 238
23.3. SMBus Operation .......................................................................................... 238
23.3.1. Transmitter Vs. Receiver....................................................................... 239
23.3.2. Arbitration.............................................................................................. 239
23.3.3. Clock Low Extension............................................................................. 239
23.3.4. SCL Low Timeout.................................................................................. 239
23.3.5. SCL High (SMBus Free) Timeout ......................................................... 240
23.4. Using the SMBus........................................................................................... 240
23.4.1. SMBus Configuration Register.............................................................. 240
23.4.2. SMB0CN Control Register .................................................................... 244
23.4.3. Data Register ........................................................................................ 247
23.5. SMBus Transfer Modes................................................................................. 247
23.5.1. Write Sequence (Master) ...................................................................... 248
23.5.2. Read Sequence (Master) ...................................................................... 249
23.5.3. Write Sequence (Slave) ........................................................................ 250
23.5.4. Read Sequence (Slave) ........................................................................ 251
23.6. SMBus Status Decoding................................................................................ 251
24. UART0 ................................................................................................................... 254
24.1. Baud Rate Generator .................................................................................... 254
24.2. Data Format................................................................................................... 256
24.3. Configuration and Operation ......................................................................... 257
24.3.1. Data Transmission ................................................................................ 257
24.3.2. Data Reception ..................................................................................... 257
24.3.3. Multiprocessor Communications ........................................................... 258
25. UART1 ................................................................................................................... 263
25.1. Enhanced Baud Rate Generation.................................................................. 264
25.2. Operational Modes ........................................................................................ 265
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