CAT24C44
256-Bit Serial Nonvolatile CMOS Static RAM
FEATURES
s
Single 5V Supply
s
Infinite EEPROM to RAM Recall
s
CMOS and TTL Compatible I/O
s
Low CMOS Power Consumption:
s
JEDEC Standard Pinouts:
–8-lead DIP
–8-lead SOIC
s
100,000 Program/Erase Cycles (EEPROM)
s
Auto Recall on Power-up
s
Commercial, Industrial and Automotive
–Active: 3mA Max.
–Standby: 30
µ
A Max.
s
Power Up/Down Protection
s
10 Year Data Retention
Temperature Ranges
DESCRIPTION
The CAT24C44 Serial NVRAM is a 256-bit nonvolatile
memory organized as 16 words x 16 bits. The high
speed Static RAM array is bit for bit backed up by a
nonvolatile EEPROM array which allows for easy trans-
fer of data from RAM array to EEPROM (STORE) and
from EEPROM to RAM (RECALL). STORE operations
are completed in 10ms max. and RECALL operations
typically within 1.5µs. The CAT24C44 features unlim-
ited RAM write operations either through external RAM
writes or internal recalls from EEPROM. Internal false
store protection circuitry prohibits STORE operations
when V
CC
is less than 3.5V (typical) ensuring EEPROM
data integrity.
The CAT24C44 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles (EEPROM) and
has a data retention of 10 years. The device is available
in JEDEC approved 8-lead plastic DIP and SOIC
packages.
PIN CONFIGURATION
DIP Package (L)
CE
SK
DI
DO
1
2
3
4
8
7
6
5
PIN FUNCTIONS
Pin Name
SOIC Package ( V)
1
2
3
4
8
7
6
5
VCC
STORE
RECALL
VSS
Function
Serial Clock
Serial Input
Serial Data Output
Chip Enable
Recall
Store
+5V
Ground
SK
DI
DO
CE
RECALL
STORE
V
CC
V
SS
VCC
CE
STORE SK
RECALL DI
VSS
DO
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-1083, Rev. T
CAT24C44
BLOCK DIAGRAM
EEPROM ARRAY
RECALL
ROW
DECODE
STATIC RAM
ARRAY
256-BIT
STORE
CONTROL
LOGIC
STORE
RECALL
CE
DI
SK
INSTRUCTION
REGISTER
COLUMN
DECODE
DO
VCC
VSS
INSTRUCTION
DECODE
4-BIT
COUNTER
MODE SELECTION
(1)(2)
Mode
Hardware Recall
(3)
Software Recall
Hardware Store
(3)
Software Store
X = Don’t Care
STORE
1
1
0
1
RECALL
0
1
1
1
Software
Instruction
NOP
RCL
NOP
STO
Write Enable
Latch
X
X
SET
SET
Previous Recall
Latch
X
X
TRUE
TRUE
POWER-UP TIMING
(4)
Symbol
VCCSR
t
pur
t
puw
Parameter
V
CC
Slew Rate
Power-Up to Read Operations
Power-Up to Write or Store Operation
Min.
0.5
Max.
0.005
200
5
Units
V/m
µs
ms
Note:
(1) The store operation has priority over all the other operations.
(2) The store operation is inhibited when V
CC
is below
≈
3.5V.
(3) NOP designates that the device is not currently executing an instruction.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. MD-1083, Rev. T
2
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT24C44
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(2)
............. –2.0 to +VCC +2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(3)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(1)
T
DR(1)
V
ZAP(1)
I
LTH(1)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
100,000
10
2000
100
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Typ.
Max.
Units
Cycles/Byte
Years
Volts
mA
D.C. OPERATING CHARACTERISTICS
V
CC
= 5V
±10%,
unless otherwise specified.
Limits
Symbol
I
CCO
I
SB
I
LI
I
LO
V
IH
V
IL
V
OH
V
OL
Parameter
Current Consumption (Operating)
Current Consumption (Standby)
Input Current
Output Leakage Current
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
2
0
2.4
0.4
Min.
Typ.
Max.
3
30
2
10
V
CC
0.8
Unit
mA
µA
µA
µA
V
V
V
V
I
OH
= –2mA
I
OL
= 4.2mA
Conditions
Inputs = 5.5V, T
A
= 0°C
All Outputs Unloaded
CE = V
IL
0
≤
V
IN
≤
5.5V
0
≤
V
OUT
≤
5.5V
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
I/O(1)
C
IN(1)
Parameter
Input/Output Capacitance
Input Capacitance
Max.
10
6
Unit
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
Note:
(1) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns.
Maximum DC voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-1083, Rev. T
CAT24C44
A.C. CHARACTERISTICS
V
CC
= 5V
±10%,
unless otherwise specified.
Symbol
F
SK
t
SKH
t
SKL
t
DS
t
DH
t
PD
t
Z
t
CES
t
CEH
t
CDS
Parameter
SK Frequency
SK Positive Pulse Width
SK Negative Pulse Width
Data Setup Time
Data Hold Time
SK Data Valid Time
CE Disable Time
CE Enable Setup Time
CE Enable Hold Time
CE De-Select Time
800
400
800
Min.
DC
400
400
400
80
375
1
Max.
1
Units
MHz
ns
ns
ns
ns
ns
µs
ns
ns
ns
C
L
= 100pF + 1TTL gate
V
OH
= 2.2V, V
OL
= 0.65V
V
IH
= 2.2V, V
IL
= 0.65V
Input rise and fall times = 10ns
Conditions
A.C. CHARACTERISTICS, Store Cycle
V
CC
= 5V
±10%,
unless otherwise specified.
Limits
Symbol
t
ST
t
STP
t
STZ
Parameter
Store Time
Store Pulse Width
Store Disable Time
200
100
Min.
Max.
10
Units
ms
ns
ns
Conditions
C
L
= 100pF + 1TTL gate
V
OH
= 2.2V, V
OL
= 0.65V
V
IH
= 2.2V, V
IL
= 0.65V
A.C. CHARACTERISTICS, Recall Cycle
V
CC
= 5V
±10%,
unless otherwise specified.
Symbol
t
RCC
t
RCP
t
RCZ
t
ORC
t
ARC
Parameter
Recall Cycle Time
Recall Pulse Width
Recall Disable Time
Recall Enable Time
Recall Data Access Time
10
1.5
Min.
2.5
500
500
Max.
Units
µs
ns
ns
ns
µs
C
L
= 100pF + 1TTL gate
V
OH
= 2.2V, V
OL
= 0.65V
V
IH
= 2.2V, V
IL
= 0.65V
Conditions
INSTRUCTION SET
Format
Instruction
WRDS
STO
WRITE
WREN
RCL
READ
X = Don’t care
A = Address bit
Start Bit
1
1
1
1
1
1
Address
XXXX
XXXX
AAAA
XXXX
XXXX
AAAA
OP Code
000
001
011
100
101
11X
Operation
Reset Write Enable Latch (Disables, Writes and Stores)
Store RAM Data in EEPROM
Write Data into RAM Address AAAA
Set Write Enable Latch (Enables, Writes and Stores)
Recall EEPROM Data into RAM
Read Data From RAM Address AAAA
Doc. No. MD-1083, Rev. T
4
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT24C44
from the device: If the
CE
pin is prematurely deselected
while shifting in an instruction, that instruction will not be
executed, and the shift register internal to the CAT24C44
will be cleared. If there are more than or less than 16
clocks during a memory data transfer, an improper data
transfer will result. The SK clock is completely static
allowing the user to stop the clock and restart it to
resume shifting of data.
Read
Upon receiving a start bit, 4 address bits, and the 3-bit
read command (clocked into the DI pin), the DO pin of
the CAT24C44 will come out of the high impedance state
and the 16 bits of data, located at the address specified
in the instructions, will be clocked out of the device.
When clocking data from the device, the first bit clocked
out (DO) is timed from the falling edge of the 8th clock,
all succeeding bits (D1–D15) are timed from the rising
edge of the clock.
Write
After receiving a start bit, 4 address bits, and the 3-bit
WRITE command, the 16-bit word is clocked into the
device for storage into the RAM memory location speci-
fied. The
CE
pin must remain high during the entire write
operation.
DEVICE OPERATION
The CAT24C44 is intended for use with standard micro-
processors. The CAT24C44 is organized as 16 registers
by 16 bits. Seven 8-bit instructions control the device’s
operating modes, the RAM reading and writing, and the
EEPROM storing and recalling. It is also possible to
control the EEPROM store and recall functions in hard-
ware with the
STORE
and
RECALL
pins. The CAT24C44
operates on a single 5V supply and will generate, on
chip, the high voltage required during a RAM to EEPROM
storing operation.
Instructions, addresses and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin remains in a high impedance state except when
outputting data from the device. The
CE
(Chip Enable)
pin must remain high during the entire data transfer.
The format for all instructions sent to the CAT24C44 is
a logical ‘1’ start bit, 4 address bits (data read or write
operations) or 4 “Don’t Care” bits (device mode opera-
tions), and a 3-bit op code (see Instruction Set). For data
write operations, the 8-bit instruction is followed by 16
bits of data. For data read instructions, DO will come out
of the high impedance state and enable 16 bits of data
to be clocked from the device. The 8th bit of the read
instruction is a “Don’t Care” bit. This is to eliminate any
bus contention that would occur in applications where
the DI and DO pins are tied together to form a common
DI/DO line. A word of caution while clocking data to and
Figure 1. RAM Read Cycle Timing
CE
1
SK
2
3
4
5
6
7
8
9
10
11
12
22
23
24
(1)
(8)
DI
1
A
A
A
A
X
1
1
DO
HIGH-Z
D0
D1
D2
D3
D14
D15
D0
Figure 2. RAM Write Cycle Timing
CE
1
SK
2
3
4
5
6
7
8
9
10
11
12
22
23
24
DI
1
A
A
A
A
1
0
1
D0
D1
D2
D3
D13
D14
D15
Note:
(1) Bit 8 of READ instruction is “Don’t Care”.
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. MD-1083, Rev. T
FPGA/CPLD
