CAT24FC01
1-kb I
2
C Serial EEPROM
FEATURES
I
400 kHz (2.5 V) and 100 kHz (1.8 V) I
2
C bus
H
GEN
FR
ALO
EE
LE
I
1,000,000 program/erase cycles
I
100 year data retention
A
D
F
R
E
E
TM
compatible
I
1.8 to 5.5 volt operation
I
Low power CMOS technology
I
8-pin DIP, 8-pin SOIC, 8-pin TSSOP and MSOP
packages
- “Green” package option available
I
256 x 8 memory organization
I
Hardware write protect
– zero standby current
I
16-byte page write buffer
I
Industrial and extended temperature ranges
I
Self-timed write cycle with auto-clear
DESCRIPTION
The CAT24FC01 is a 1-kb Serial CMOS EEPROM
internally organized as 128 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces
device power requirements.
The CAT24FC01 features a 16-byte page write buffer.
The device operates via the I
2
C bus serial interface and
is available in 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and
MSOP packages.
PIN CONFIGURATION
DIP Package (P, L)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
BLOCK DIAGRAM
SOIC Package (J, W)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
EXTERNAL LOAD
DOUT
ACK
VCC
VSS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SENSE AMPS
SHIFT REGISTERS
TSSOP Package (U, Y)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
SDA
START/STOP
LOGIC
XDEC
WP
CONTROL
LOGIC
E
2
PROM
MSOP Package (R, Z)
DATA IN STORAGE
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
HIGH VOLTAGE/
TIMING CONTROL
PIN FUNCTIONS
Pin Name
A0, A1, A2
SDA
SCL
WP
V
CC
V
SS
Function
Device Address Inputs
Serial Data/Address
Serial Clock
Write Protect
1.8 V to 5.5 V Power Supply
Ground
* Catalyst Semiconductor is licensed by Philips Corporation to carry
the I
2
C Bus Protocol.
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc No. 1073, Rev. A
CAT24FC01
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
–55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
............ –2.0 V to V
CC
+ 2.0 V
V
CC
with Respect to Ground ............. –2.0 V to +7.0 V
Package Power Dissipation
Capability (T
A
= 25°C) .................................. 1.0 W
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Lead Soldering Temperature (10 seconds) ...... 300°C
Output Short Circuit Current
(2)
....................... 100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
4000
100
Typ
Max
Units
Cycles/Byte
Years
Volts
mA
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, unless otherwise specified.
Symbol
I
CC
I
CC
I
SB(5)
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Parameter
Power Supply Current (Read)
Power Supply Current (Write)
Standby Current (V
CC
= 5.0 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3.0 V)
Output Low Voltage (V
CC
= 1.8 V)
Test Conditions
f
SCL
= 100 kHz
f
SCL
= 100 kHz
V
IN
= GND or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
Min
Typ
1
3
0
1
1
Max
Units
mA
mA
µA
µA
µA
–1
V
CC
x 0.7
I
OL
= 3 mA
I
OL
= 1.5 mA
0.4
0.5
V
CC
x 0.3
V
CC
+ 1.0
V
V
V
V
CAPACITANCE
T
A
= 25°C, f = 400 kHz, V
CC
= 5 V
Symbol
C
I/O(3)
C
IN(3)
Test
Input/Output Capacitance (SDA)
Input Capacitance (other pins)
Conditions
V
I/O
= 0 V
V
IN
= 0 V
Min
Typ
Max
8
6
Units
pF
pF
Note:
(1) The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1.0 V to V
CC
+ 1.0 V.
(5) Standby Current, I
SB
= 0
µA
(<900 nA).
Doc. No. 1073, Rev. A
2
CAT24FC01
A.C. CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
1.8 V - 5.5 V
Min
F
SCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
Clock Frequency
Noise Suppression Time
Constant at SCL, SDA Inputs
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
4
100
4.7
4
4.7
4
4.7
0
250
1
300
0.6
100
0
Max
100
100
3.5
1.3
0.6
1.3
0.6
0.6
0
100
0.3
300
2.5 V - 5.5 V
Min
0
Max
400
100
0.9
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Power-Up Timing
(1)(2)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
Write Cycle Limits
Symbol
t
WR
Parameter
Write Cycle Time
Min
Typ
Max
5
Units
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
3
Doc No. 1073, Rev. A
CAT24FC01
FUNCTIONAL DESCRIPTION
The CAT24FC01 supports the I
2
C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. Data
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24FC01 operates as
a Slave device. Both the Master and Slave devices can
operate as either transmitter or receiver, but the Master
device controls which mode is activated. A maximum of
8 devices may be connected to the bus as determined by
the device address inputs A0, A1, and A2.
SDA:
Serial Data/Address
The CAT24FC01 bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
A0, A1, A2:
Device Address Inputs
These inputs set device address when cascading multiple
devices. A maximum of eight devices can be cascaded
when using the device.
WP:
Write Protect
This input, when tied to GND, allows write operations to
the entire memory. For CAT24FC01 when this pin is tied
to V
CC
, the entire array of memory is write protected.
When left floating, memory is unprotected.
PIN DESCRIPTIONS
SCL:
Serial Clock
The CAT24FC01 serial clock input pin is used to clock all
data transfers into or out of the device. This is an input pin.
Figure 1. Bus Timing
tF
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tHIGH
tR
tLOW
tSU:DAT
tSU:STO
SDA IN
tAA
SDA OUT
tDH
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Doc. No. 1073, Rev. A
4
CAT24FC01
I
2
C BUS PROTOCOL
The following defines the features of the I
2
C bus proto-
col:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC01 monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
and define which device the Master is accessing. Up to
eight CAT24FC01 may be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24FC01 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC01 then performs a Read or a Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24FC01 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
When the CAT24FC01 begins a READ mode, it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT24FC01 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 for the CAT24FC01 (see Fig. 5). The next three
significant bits (A2, A1, A0) are the device address bits
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
A2
A1
A0
R/W
Normal Read and Write
DEVICE ADDRESS
5
Doc No. 1073, Rev. A
FPGA/CPLD
