CAT5111
100-Tap Digitally Program-
mable Potentiometer (DPPt)
with Buffered Wiper
Description
The CAT5111 is a single digitally programmable potentiometer
(DPPt) designed as an electronic replacement for mechanical
potentiometers. Ideal for automated adjustments on high volume
production lines, they are also well suited for applications where
equipment requiring periodic adjustment is either difficult to access or
located in a hazardous or remote environment.
The CAT5111 contains a 100−tap series resistor array connected
between two terminals R
H
and R
L
. An up/down counter and decoder
that are controlled by three input pins, determines which tap is
connected to the wiper, R
WB
. The CAT5111 wiper is buffered by an op
amp that operates rail to rail. The wiper setting, stored in non−volatile
memory, is not lost when the device is powered down and is
automatically recalled when power is returned. The wiper can be
adjusted to test new system values without effecting the stored setting.
Wiper−control of the CAT5111 is accomplished with three input
control pins, CS, U/D, and INC. The INC input increments the wiper
in the direction which is determined by the logic state of the U/D input.
The CS input is used to select the device and also store the wiper
position prior to power down.
The digitally programmable potentiometer can be used as a buffered
voltage divider. For applications where the potentiometer is used as a
2−terminal variable resistor, please refer to the CAT5113. The
buffered wiper of the CAT5111 is not compatible with that application.
Features
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SOIC−8
V SUFFIX
CASE 751BD
MSOP−8
Z SUFFIX
CASE 846AD
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATIONS
INC
U/D
R
H
GND
1
V
CC
CS
R
L
R
WB
PDIP (L), SOIC (V),
MSOP (Z)
CS
V
CC
INC
U/D
1
R
L
R
WB
GND
R
H
TSSOP (Y)
(Top Views)
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100−position Linear Taper Potentiometer
Non−volatile EEPROM Wiper Storage; Buffered Wiper
Low Power CMOS Technology
Single Supply Operation: 2.5 V
−
6.0 V
Increment Up/Down Serial Interface
Resistance Values: 10 kW, 50 kW and 100 kW
Available in PDIP, SOIC, TSSOP and MSOP Packages
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Automated Product Calibration
Remote Control Adjustments
Offset, Gain and Zero Control
Tamper−proof Calibrations
Contrast, Brightness and Volume Controls
Motor Controls and Feedback Systems
Programmable Analog Functions
PIN FUNCTION
Pin Name
INC
U/D
R
H
GND
R
WB
R
L
CS
V
CC
Function
Increment Control
Up/Down Control
Potentiometer High Terminal
Ground
Buffered Wiper Terminal
Potentiometer Low Terminal
Chip Select
Supply Voltage
Applications
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ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
©
Semiconductor Components Industries, LLC, 2010
August, 2010
−
Rev. 18
1
Publication Order Number:
CAT5111/D
CAT5111
DEVICE MARKING INFORMATION
PDIP
SOIC
MSOP
TSSOP
RL4A
CAT5111LT
YMXXXX
RL4A
CAT5111VT
YMXXXX
AARL
YMP
A1RL
4YMXXX
R = Resistance:
AARL = CAT5111ZI−10−T3
AAPT = CAT5111ZI−50−T3
2 = 10 kW
AAPX = CAT5111ZI−00−T3
4 = 50 kW
Y = Production Year (Last Digit)
5 = 100 kW
M = Production Month (1−9, A, B, C)
L = Assembly Location
P = Product Revision
4 = Lead Finish
−
NiPdAu
A = Product Revision (Fixed as “A”)
CAT5111L = Device Code (PDIP)
CAT5111V = Device Code (SOIC)
T = Temperature Range (Industrial)
Y = Production Year (Last Digit)
M = Production Month (1−9, A, B, C)
XXXX = Last Four Digits of Assembly Lot Number
A1 = Device Code
R = Resistance:
2 = 10 kW
4 = 50 kW
5 = 100 kW
L = Assembly Location
4 = Lead Finish
−
NiPdAu
Y = Production Year (Last Digit)
M = Production Month (1−9, A, B, C)
XXX = Last Three Digits of
XXX =
Assembly Lot Number
R
H
V
CC
R
H
U/D
INC
CS
Power On Recall
GND
Control
and
Memory
+
–
R
WB
+
–
R
L
R
L
R
WB
Figure 1. Functional Diagram
Figure 2. Electronic Potentiometer Implementation
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CAT5111
Pin Description
INC:
Increment Control Input
The INC input (on the falling edge) moves the wiper in the
up or down direction determined by the condition of the U/D
input.
U/D:
Up/Down Control Input
The U/D input controls the direction of the wiper movement.
When in a high state and CS is low, any high−to−low
transition on INC will cause the wiper to move one
increment toward the R
H
terminal. When in a low state and
CS is low, any high−to−low transition on INC will cause the
wiper to move one increment towards the R
L
terminal.
R
H
:
High End Potentiometer Terminal
R
H
is the high end terminal of the potentiometer. It is not
required that this terminal be connected to a potential greater
than the R
L
terminal. Voltage applied to the R
H
terminal
cannot exceed the supply voltage, V
CC
or go below ground,
GND.
R
WB
:
Wiper Potentiometer Terminal (Buffered)
R
WB
is the buffered wiper terminal of the potentiometer. Its
position on the resistor array is controlled by the control
inputs, INC, U/D and CS.
R
L
:
Low End Potentiometer Terminal
R
L
is the low end terminal of the potentiometer. It is not
required that this terminal be connected to a potential less
than the R
H
terminal. Voltage applied to the R
L
terminal
cannot exceed the supply voltage, V
CC
or go below ground,
GND. R
L
and R
H
are electrically interchangeable.
CS:
Chip Select
The chip select input is used to activate the control input of
the CAT5111 and is active low. When in a high state, activity
on the INC and U/D inputs will not affect or change the
position of the wiper.
Device Operation
The CAT5111 operates like a digitally controlled
potentiometer with R
H
and R
L
equivalent to the high and low
terminals and R
WB
equivalent to the mechanical
potentiometer’s wiper. There are 100 available tap positions
including the resistor end points, R
H
and R
L
. There are 99
resistor elements connected in series between the R
H
and R
L
terminals. The wiper terminal is connected to one of the 100
taps and controlled by three inputs, INC, U/D and CS. These
inputs control a seven−bit up/down counter whose output is
decoded to select the wiper position. The selected wiper
position can be stored in nonvolatile memory using the INC
and CS inputs.
With CS set LOW the CAT5111 is selected and will
respond to the U/D and INC inputs. HIGH to LOW
transitions on INC will increment or decrement the wiper
(depending on the state of the U/D input and seven−bit
counter). The wiper, when at either fixed terminal, acts like
its mechanical equivalent and does not move beyond the last
position. The value of the counter is stored in nonvolatile
memory whenever CS transitions HIGH while the INC input
is also HIGH. When the CAT5111 is powered−down, the last
stored wiper counter position is maintained in the
nonvolatile memory. When power is restored, the contents
of the memory are recalled and the counter is set to the value
stored.
With INC set low, the CAT5111 may be de−selected and
powered down without storing the current wiper position in
nonvolatile memory. This allows the system to always
power up to a preset value stored in nonvolatile memory.
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CAT5111
Table 1. OPERATION MODES
INC
High to Low
High to Low
High
Low
X
CS
Low
Low
Low to High
Low to High
High
U/D
High
Low
X
X
X
R
H
C
H
Operation
Wiper toward R
H
Wiper toward R
L
Store Wiper Position
No Store, Return to Standby
Standby
R
WI
R
WB
C
W
C
L
R
L
Figure 3. Potentiometer Equivalent Circuit
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Supply Voltage
V
CC
to GND
Inputs
CS to GND
INC to GND
U/D to GND
R
H
to GND
R
L
to GND
R
WB
to GND
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix)
Industrial (‘I’ suffix)
Junction Temperature
Storage Temperature
Lead Soldering (10 s max)
Ratings
−0.5
to +7
−0.5
to V
CC
+0.5
−0.5
to V
CC
+0.5
−0.5
to V
CC
+0.5
−0.5
to V
CC
+0.5
−0.5
to V
CC
+0.5
−0.5
to V
CC
+0.5
0 to 70
−40
to +85
+150
−65
to 150
+300
Units
V
V
V
V
V
V
V
°C
°C
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. RELIABILITY CHARACTERISTICS
Symbol
V
ZAP
(Note 1)
I
LTH
(Notes 1, 2)
T
DR
N
END
Parameter
ESD Susceptibility
Latch−Up
Data Retention
Endurance
Test Method
MIL−STD−883, Test Method 3015
JEDEC Standard 17
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 1003
Min
2000
100
100
1,000,000
Typ
Max
Units
V
mA
Years
Stores
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch−up protection is provided for stresses up to 100 mA on address and data pins from
−1
V to V
CC
+ 1 V
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CAT5111
Table 4. DC ELECTRICAL CHARACTERISTICS
(V
CC
= +2.5 V to +6 V unless otherwise specified)
Symbol
POWER SUPPLY
V
CC
I
CC1
I
CC2
I
SB1
(Note 4)
LOGIC INPUTS
I
IH
I
IL
V
IH1
V
IL1
V
IH2
V
IL2
R
POT
Input Leakage Current
Input Leakage Current
TTL High Level Input Voltage
TTL Low Level Input Voltage
CMOS High Level Input Voltage
CMOS Low Level Input Voltage
2.5 V
≤
V
CC
≤
6 V
V
IN
= V
CC
V
IN
= 0 V
4.5 V
≤
V
CC
≤
5.5 V
–
–
2
0
V
CC
x 0.7
−0.3
–
–
–
–
–
–
10
−10
V
CC
0.8
V
CC
+ 0.3
V
CC
x 0.2
mA
mA
V
V
V
V
Operating Voltage Range
Supply Current (Increment)
V
CC
= 6 V, f = 1 MHz, I
W
= 0
V
CC
= 6 V, f = 250 kHz, I
W
= 0
Supply Current (Write)
Programming, V
CC
= 6 V
V
CC
= 3 V
Supply Current (Standby)
CS = V
CC
−
0.3 V
U/D, INC = V
CC
−
0.3 V or GND
2.5
–
–
–
–
–
–
–
–
–
–
75
6
200
100
1000
500
150
V
mA
mA
mA
mA
mA
Parameter
Conditions
Min
Typ
Max
Units
POTENTIOMETER CHARACTERISTICS
Potentiometer Resistance
−10
Device
−50
Device
−00
Device
Pot. Resistance Tolerance
V
RH
V
RL
INL
DNL
R
OUT
I
OUT
TC
RPOT
TC
RATIO
C
RH
/C
RL
/C
RW
fc
V
WB(SWING)
3.
4.
5.
6.
Voltage on R
H
pin
Voltage on R
L
pin
Resolution
Integral Linearity Error
Differential Linearity Error
Buffer Output Resistance
Buffer Output Current
TC of Pot Resistance
Ratiometric TC
Potentiometer Capacitances
Frequency Response
Output Voltage Range
Passive Attenuator, 10 kW
I
OUT
≤
100
mA,
V
CC
= 5 V
0.01 V
CC
8/8/25
1.7
0.99 V
CC
I
W
≤
2
mA
I
W
≤
2
mA
0.05 V
CC
≤
V
WB
≤
0.95 V
CC
,
V
CC
= 5 V
0.05 V
CC
≤
V
WB
≤
0.95 V
CC
,
V
CC
= 5 V
300
20
0
0
1
0.5
0.25
1
0.5
1
3
10
50
100
±20
V
CC
V
CC
%
V
V
%
LSB
LSB
W
mA
ppm/°C
ppm/°C
pF
MHz
kW
This parameter is tested initially and after a design or process change that affects the parameter.
Latch−up protection is provided for stresses up to 100 mA on address and data pins from
−1
V to V
CC
+ 1 V
I
W
= source or sink
These parameters are periodically sampled and are not 100% tested.
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