CAT6095
Digital Output Temperature
Sensor
Description
The CAT6095 is a JEDEC JC42.4 compliant Temperature Sensor
designed for general purpose temperature measurements requiring a
digital output.
The CAT6095 measures temperature at least 10 times every second.
Temperature readings can be retrieved by the host via the serial
interface, and are compared to high, low and critical trigger limits
stored into internal registers. Over or under limit conditions can be
signaled on the open−drain EVENT pin.
The CAT6095 is packaged in space saving TDFN package with
exposed backside die attach pads (DAP). The exposed DAP reduces
overall thermal resistance, thus providing faster response to thermal
changes when compared to SOIC, TSSOP or SOT packages.
Features
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TDFN−8
VP2 SUFFIX
CASE 511AK
PIN CONFIGURATION
A
0
A
1
A
2
V
SS
(Top View)
For the location of Pin 1, please consult the
corresponding package drawing.
1
V
CC
EVENT
SCL
SDA
•
•
•
•
•
JEDEC JC42.4 Compliant Temperature Sensor
Temperature Range:
−40°C
to +125°C
Supply Range: 3.3 V
±
10%
I
2
C / SMBus Interface
Schmitt Triggers and Noise Suppression Filters on SCL and SDA
Inputs
•
Low Power CMOS Technology
•
2 x 3 x 0.75 mm TDFN Package
•
These Devices are Pb−Free and are RoHS Compliant
V
CC
MARKING DIAGRAM
HMC
ALL
YM
G
HMC
A
LL
Y
M
G
= Specific Device Code
= Assembly Location Code
= Assembly Lot Number (Last Two Digits)
= Production Year (Last Digit)
= Production Month (1
−
9, O, N, D)
= Pb−Free Package
SCL
CAT6095
A
2
, A
1
, A
0
SDA
EVENT
PIN FUNCTIONS
Pin Name
V
SS
A
0
, A
1
, A
2
SDA
SCL
EVENT
V
CC
V
SS
DAP
Function
Device Address Input
Serial Data Input/Output
Serial Clock Input
Open−drain Event Output
Power Supply
Ground
Backside Exposed DAP at V
SS
Figure 1. Functional Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
©
Semiconductor Components Industries, LLC, 2011
May, 2011
−
Rev. 5
1
Publication Order Number:
CAT6095/D
CAT6095
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Voltage on any pin with respect to Ground (Note 1)
Rating
−45
to +130
−65
to +150
−0.5
to +6.5
Units
°C
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. The A
0
pin can be raised to a HV level compatible
with the use of a DDR3 SPD device sharing the bus with the TS. SCL and SDA inputs can be raised to the maximum limit, irrespective of V
CC
.
Table 2. TEMPERATURE CHARACTERISTICS
(V
CC
= 3.3 V
±
10%, T
A
=
−40°C
to +125°C, unless otherwise specified)
Parameter
Temperature Reading Error
Class B, JC42.4 compliant
Test Conditions/Comments
+75°C
≤
T
A
≤
+95°C, active range
+40°C
≤
T
A
≤
+125°C, monitor range
−20°C
≤
T
A
≤
+125°C, sensing range
ADC Resolution
Temperature Resolution
Temperature Conversion Time
Thermal Resistance (Note 2)
q
JA
Junction−to−Ambient (Still Air)
Max
±1.0
±2.0
±3.0
12
0.0625
100
92
Unit
°C
°C
°C
Bits
°C
ms
°C/W
2. Power Dissipation is defined as P
J
= (T
J
−
T
A
)/q
JA
, where T
J
is the junction temperature and T
A
is the ambient temperature. The thermal
resistance value refers to the case of a package being used on a standard 2−layer PCB.
Table 3. D.C. OPERATING CHARACTERISTICS
(V
CC
= 3.3 V
±
10%, T
A
=
−40°C
to +125°C, unless otherwise specified)
Symbol
I
CC
I
SHDN
I
L
V
IL
V
IH
V
OL
I/O Pin Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
I
OL
= 3 mA, V
CC
> 2.5 V
Parameter
Supply Current
Test Conditions/Comments
TS active
TS shut−down; no bus activity
Pin at GND or V
CC
−0.5
0.7 x V
CC
Min
Max
200
10
2
0.3 x V
CC
V
CC
+ 0.5
0.4
Unit
mA
mA
mA
V
V
V
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2
CAT6095
Table 4. A.C. CHARACTERISTICS
(V
CC
= 3.3 V
±
10%, T
A
=
−40°C
to +125°C) (Note 3)
Symbol
F
SCL
(Note 4)
t
HIGH
t
LOW
t
TIMEOUT
(Note 4)
t
R
(Note 5)
t
F
(Note 5)
t
SU:DAT
(Note 6)
t
HD:DAT
(Note 5)
t
SU:STA
t
HD:STA
t
SU:STO
t
BUF
T
i
t
PU
(Note 7)
Clock Frequency
High Period of SCL Clock
Low Period of SCL Clock
SMBus SCL Clock Low Timeout
SDA and SCL Rise Time
SDA and SCL Fall Time
Data Setup Time
Data Hold Time (for Input Data)
Data Hold Time (for Output Data)
START Condition Setup Time
START Condition Hold Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
Noise Pulse Filtered at SCL and SDA Inputs
Power−up Delay to Valid Temperature Recording
100
0
300
600
600
600
1300
100
100
900
Parameter
Min
10
600
1300
25
35
300
300
Max
400
Units
kHz
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
3. Timing reference points are set at 30%, respectively 70% of V
CC
, as illustrated in Figure 11. Bus loading must be such as to allow meeting
the V
IL
, V
OL
as well as the various timing limits.
4. The TS interface will reset itself and will release the SDA line if the SCL line stays low beyond the t
TIMEOUT
limit. The time−out count is started
(and then re−started) on every negative transition of SCL in the time interval between START and STOP.
5. In a “Wired−OR” system (such as I
2
C or SMBus), SDA rise time is determined by bus loading. Since each bus pull−down device must be
able to sink the (external) bus pull−up current (in order to meet the V
IL
and/or V
OL
limits), it follows that SDA fall time is inherently faster than
SDA rise time. SDA rise time can exceed the standard recommended t
R
limit, as long as it does not exceed t
LOW
−
t
HD:DAT
−
t
SU:DAT
, where
t
LOW
and t
HD:DAT
are actual values (rather than spec limits). A shorter t
HD:DAT
leaves more room for a longer SDA t
R
, allowing for a more
capacitive bus or a larger bus pull−up resistor. At the minimum t
LOW
spec limit of 1300 ns, the maximum t
HD:DAT
of 900 ns demands a
maximum SDA t
R
of 300 ns. The CAT6095’s maximum t
HD:DAT
is <700 ns, thus allowing for an SDA t
R
of up to 500 ns at minimum t
LOW
.
6. The minimum t
SU:DAT
of 100 ns is a limit recommended by standards. The TS will accept a t
SU:DAT
of 0 ns.
7. The first valid temperature recording can be expected after t
PU
at nominal supply voltage.
Table 5. PIN CAPACITANCE
(T
A
= 25°C, V
CC
= 3.3 V, f = 1 MHz)
Symbol
C
IN
Parameter
SDA, EVENT Pin Capacitance
Input Capacitance (other pins)
Test Conditions/Comments
V
IN
= 0
V
IN
= 0
Min
Max
8
6
Unit
pF
pF
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CAT6095
TYPICAL PERFORMANCE CHARACTERISTICS
(V
CC
= 3.3 V, T
A
=
−25°C
to +125°C, unless otherwise specified.)
300
250
200
150
100
50
0
−25
I
SHDN
(mA)
0
25
50
T
AMB
(°C)
75
100
125
I
CC
(mA)
5
4
3
2
1
0
−1
−25
0
25
50
T
AMB
(°C)
75
100
125
Figure 2. Active Current (I
2
C−bus Idle)
4
3
2
DT
(°C)
1
0
−1
−2
−3
−4
−25
0
25
50
T
AMB
(°C)
75
100
125
Part # 1
Part # 2
T
CONV
(ms)
80
70
60
50
40
30
20
−25
(I
2
C−bus
Figure 3. Standby Current
Idle, TS Shut−down)
0
25
50
T
AMB
(°C)
75
100
125
Figure 4. Temperature Read−Out Error
3.0
2.6
2.2
1.8
1.4
1.0
−25
t
TIMEOUT
(ms)
40
Figure 5. A/D Conversion Time
35
V
TH
(V)
30
25
0
25
50
T
AMB
(°C)
75
100
125
20
−25
0
25
50
T
AMB
(°C)
75
100
125
Figure 6. POR Threshold Voltage
Figure 7. SMBus SCL Clock Low Timeout
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CAT6095
Pin Description
SCL:
The Serial Clock input pin accepts the Serial Clock
generated by the Master (Host).
SDA:
The Serial Data I/O pin receives input data and
transmits data stored in the internal registers. In transmit
mode, this pin is open drain. Data is acquired on the positive
edge, and is delivered on the negative edge of SCL.
A0, A1 and A2:
The Address pins set the device address.
These pins have on−chip pull−down resistors.
EVENT:
The open−drain EVENT pin can be programmed
to signal over/under temperature limit conditions.
Power−On Reset
The CAT6095 incorporates Power−On Reset (POR)
circuitry which monitors the supply voltage, and then resets
(initializes) the internal state machine below a POR trigger
level of approximately 2.0 V, i.e. well below the minimum
recommended V
CC
value.
The temperature sensor (TS) powers-up into conversion
mode. The internal state machine will operate properly
above the POR trigger level, but valid temperature readings
can be expected only after the first conversion cycle started
and completed at nominal supply voltage.
Device Interface
The CAT6095 supports I
2
C and SMBus data transmission
protocols. These protocols describe serial communication
between transmitters and receivers sharing a 2−wire data
bus. Data
flow
is controlled by a Master device, which
generates the serial clock and the START and STOP
conditions. The CAT6095 acts as a Slave device. Master and
Slave alternate as transmitter and receiver. Up to 8 CAT6095
devices may be present on the bus simultaneously, and can
be individually addressed by matching the logic state of the
address inputs A0, A1, and A2.
I
2
C/SMBus Protocol
The I
2
C/SMBus uses two ‘wires’, one for clock (SCL) and
one for data (SDA). The two wires are connected to the V
CC
supply via pull−up resistors. Master and Slave devices
connect to the bus via their respective SCL and SDA pins.
The transmitting device pulls down the SDA line to
‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 8).
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake−up’ call to all Slaves. Absent a
START, a Slave will not respond to commands.
STOP
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP tells the Slave that no more data will be written
to or read from the Slave.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. The first 4 bits of the Slave address (the
preamble) select the Temperature Sensor (TS preamble =
0011) as shown in Figure 9. The next 3 bits, A2, A1 and A0,
select one of 8 possible TS Slave devices. The last bit, R/W,
specifies whether a Read (1) or Write (0) operation is being
performed.
Acknowledge
A matching Slave address is acknowledged (ACK) by the
Slave by pulling down the SDA line during the 9
th
clock
cycle (Figure 10). After that, the Slave will acknowledge all
data bytes sent to the bus by the Master. When the Slave is
the transmitter, the Master will in turn acknowledge data
bytes in the 9
th
clock cycle. The Slave will stop transmitting
after the Master does not respond with acknowledge
(NoACK) and then issues a STOP. Bus timing is illustrated
in Figure 11.
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