CAT93C46/56/57/66/86
1K/2K/2K/4K/16K-Bit Microwire Serial E
2
PROM
FEATURES
s
High Speed Operation:
s
Power-Up Inadvertant Write Protection
s
1,000,000 Program/Erase Cycles
s
100 Year Data Retention
s
Commercial, Industrial and Automotive
– 93C46/56/57/66: 1MHz
– 93C86: 3MHz
s
Low Power CMOS Technology
s
1.8 to 6.0 Volt Operation
s
Selectable x8 or x16 Memory Organization
s
Self-Timed Write Cycle with Auto-Clear
s
Hardware and Software Write Protection
Temperature Ranges
s
Sequential Read (except 93C46)
s
Program Enable (PE) Pin (93C86 only)
DESCRIPTION
The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit
Serial E
2
PROM memory devices which are configured
as either registers of 16 bits (ORG pin at V
CC
) or 8 bits
(ORG pin at GND). Each register can be written (or read)
serially by using the DI (or DO) pin. The CAT93C46/56/
57/66/86 are manufactured using Catalyst’s advanced
CMOS E
2
PROM floating gate technology. The devices
are designed to endure 1,000,000 program/erase cycles
and have a data retention of 100 years. The devices are
available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP
packages.
PIN CONFIGURATION
DIP Package (P)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
SOIC Package (J)
1
2
3
4
8
7
6
5
ORG
GND
DO
DI
SOIC Package (S)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
SOIC Package (K)
1
2
3
4
8
7
6
5
VCC
NC (PE*)
ORG
GND
TSSOP Package (U)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC (PE*)
ORG
GND
VCC
NC (PE*)
NC (PE*)
VCC
ORG
CS
GND
SK
VCC
CS
NC (PE*) SK
ORG
DI
GND
DO
*Only For 93C86
PIN FUNCTIONS
Pin Name
CS
SK
DI
DO
V
CC
GND
ORG
NC
PE*
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
+1.8 to 6.0V Power Supply
Ground
Memory Organization
No Connection
Program Enable
93C46/56/57/66/86
F01
BLOCK DIAGRAM
VCC
GND
ORG
MEMORY ARRAY
ORGANIZATION
ADDRESS
DECODER
DATA
REGISTER
DI
CS
PE*
MODE DECODE
LOGIC
OUTPUT
BUFFER
Note: When the ORG pin is connected to VCC, the X16 organiza
tion is selected. When it is connected to ground, the X8 pin
is selected. If the ORG pin is left unconnected, then an
internal pullup device will select the X16 organization.
SK
CLOCK
GENERATOR
DO
93C46/56/57/66/86 F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25056-00 2/98 M-1
93C46/56/57/66/86
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to Ground
(1)
............ –2.0V to +V
CC
+2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
1,000,000
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol
I
CC1
I
CC2
I
SB1
I
SB2(5)
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Power Supply Current
(Standby) (x8 Mode)
Power Supply Current
(Standby) (x16Mode)
Input Leakage Current
Output Leakage Current
(Including ORG pin)
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
V
CC
-0.2
2.4
0.2
-0.1
2
0
V
CC
X0.7
Min.
Typ.
Max.
3
500
10
0
1
1
0.8
V
CC
+1
V
CC
X0.2
V
CC
+1
0.4
Units
mA
µA
µA
µA
µA
µA
Test Conditions
f
SK
= 1MHz
V
CC
= 5.0V
f
SK
= 1MHz
V
CC
= 5.0V
CS = 0V
ORG=GND
CS=0V
ORG=Float or V
CC
V
IN
= 0V to V
CC
V
OUT
= 0V to V
CC
,
CS = 0V
4.5V≤V
CC
<5.5V
V
V
V
V
V
V
1.8V≤V
CC
<2.7V
4.5V≤V
CC
<5.5V
I
OL
= 2.1mA
I
OH
= -400µA
1.8V≤V
CC
<2.7V
V
I
OL
= 1mA
I
OH
= -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) Standby Current (ISB
2
)=0µA (<900nA) for 93C46/56/57/66, (ISB
2
)=2µA for 93C86.
Doc. No. 25056-00 2/98 M-1
2
93C46/56/57/66/86
PIN CAPACITANCE
Symbol
C
OUT(3)
C
IN(3)
Test
OUTPUT CAPACITANCE (DO)
INPUT CAPACITANCE (CS, SK, DI, ORG)
Max.
5
5
Units
pF
pF
Conditions
V
OUT
=OV
V
IN
=OV
INSTRUCTION SET
Instruction Device
Type
READ
93C46
93C56
(1)
93C66
93C57
93C86
93C46
93C56
(1)
93C66
93C57
93C86
93C46
93C56
(1)
93C66
93C57
93C86
93C46
93C56
93C66
93C57
93C86
93C46
93C56
93C66
93C57
93C86
93C46
93C56
93C66
93C57
93C86
93C46
93C56
93C66
93C57
93C86
Start Opcode
Bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
10
10
10
10
10
11
11
11
11
11
01
01
01
01
01
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Address
x8
x16
A6-A0
A8-A0
A8-A0
A7-A0
A10-A0
A6-A0
A8-A0
A8-A0
A7-A0
A10-A0
A6-A0
A8-A0
A8-A0
A7-A0
A10-A0
11XXXXX
11XXXXXXX
11XXXXXXX
Data
x8
x16
Comments
Read Address AN–A0
PE
(2)
A5-A0
A7-A0
A7-A0
A6-A0
A9-A0
A5-A0
A7-A0
A7-A0
A6-A0
A9-A0
A5-A0
A7-A0
A7-A0
A6-A0
A9-A0
11XXXX
11XXXXXX
11XXXXXX
X
Clear Address AN–A0
ERASE
I
D7-D0
D7-D0
D7-D0
D7-D0
D7-D0
D15-D0
D15-D0
D15-D0
D15-D0
D15-D0
Write Address AN–A0
WRITE
I
Write Enable
EWEN
11XXXXXX
11XXXXX
11XXXXXXXXX 11XXXXXXXX
00XXXXX
00XXXXXXX
00XXXX
00XXXXXX
X
Write Disable
EWDS
00XXXXXXX
00XXXXXX
00XXXXXX
00XXXXX
00XXXXXXXXX 00XXXXXXXX
10XXXXX
10XXXXXXX
10XXXXXXX
10XXXXXX
10XXXX
10XXXXXX
10XXXXXX
10XXXXX
X
Clear All Addresses
ERAL
10XXXXXXXXX 10XXXXXXXX
01XXXXX
01XXXXXXX
01XXXXXXX
01XXXX
01XXXXXX
01XXXXXX
I
D7-D0
D7-D0
D7-D0
D7-D0
D7-D0
D15-D0
D15-D0
D15-D0
D15-D0
D15-D0
Write All Addresses
WRAL
01XXXXXX
01XXXXX
01XXXXXXXXX 01XXXXXXXX
I
Note:
(1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE
and ERASE commands.
(2) Applicable only to 93C86
(3) This parameter is tested initially and after a design or process change that affects the parameter.
3
Doc. No. 25056-00 2/98 M-1
93C46/56/57/66/86
A.C. CHARACTERISTICS (93C46/56/57/66)
Limits
V
CC
=
1.8V-6V*
SYMBOL PARAMETER
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ(1)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
1
1
1
1
250
DC
Min.
200
0
400
400
1
1
400
10
0.5
0.5
0.5
0.5
500
DC
Max.
V
CC
=
2.5V-6V
Min.
100
0
200
200
0.5
0.5
200
10
0.25
0.25
0.25
0.25
1000
Max.
V
CC
=
4.5V-5.5V
Min.
50
0
100
100
0.25
0.25
100
10
Max.
UNITS
ns
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
KHZ
C
L
= 100pF
V
IL
= 0.45V
V
IH
= 2.4V
C
L
= 100pF
V
OL
= 0.8V
V
OH
= 2.0v
C
L
= 100pF
Test
Conditions
* Preliminary data for 93C56/57/66
A.C. CHARACTERISTICS (93C86)
Limits
V
CC
=
1.8V-6V*
SYMBOL PARAMETER
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ(1)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
1
1
1
1
250
DC
Min.
200
0
400
400
1
1
400
5
0.5
0.5
0.5
0.5
1000
DC
Max.
V
CC
=
2.5V-6V
Min.
150
0
250
250
0.5
0.5
200
5
0.1
0.1
0.1
0.1
3000
Max.
V
CC
=
4.5V-5.5V
Min.
50
0
50
50
0.1
0.1
100
5
Max.
UNITS
ns
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
KHZ
C
L
= 100pF
V
IL
= 0.45V
V
IH
= 2.4V
C
L
= 100pF
V
OL
= 0.8V
V
OH
= 2.0v
C
L
= 100pF
Test
Conditions
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25056-00 2/98 M-1
4
93C46/56/57/66/86
DEVICE OPERATION
The CAT93C46/56(57)66/86 is a 1024/2048/4096/
16,384-bit nonvolatile memory intended for use with
industry standard microprocessors. The CAT93C46/56/
57/66/86 can be organized as either registers of 16 bits
or 8 bits. When organized as X16, seven 9-bit instruc-
tions for 93C46; seven 10-bit instructions for 93C57;
seven 11-bit instructions for 93C56 and 93C66; seven
13-bit instructions for 93C86; control the reading, writing
and erase operations of the device. When organized as
X8, seven 10-bit instructions for 93C46; seven 11-bit
instructions for 93C57; seven 12-bit instructions for
93C56 and 93C66: seven 14-bit instructions for 93C86;
control the reading, writing and erase operations of the
device. The CAT93C46/56/57/66/86 operates on a single
power supply and will generate on chip, the high voltage
required during any write operation.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state on
the falling edge of the clock (SK). Placing the DO pin into
the high impedance state is recommended in applica-
tions where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
Figure 1. Sychronous Data Timing
tSKHI
SK
tDIS
DI
tCSS
CS
tDIS
DO
tPD0,tPD1
DATA VALID
tCSMIN
VALID
VALID
tDIH
tSKLOW
tCSH
93C46/56/57/66/86 F03
Figure 2a. Read Instruction Timing (93C46)
SK
tCS
CS
STANDBY
AN
DI
1
1
0
tHZ
0
DN
DN–1
D1
D0
93C46/56/57/66/86 F04
AN–1
A0
DO
HIGH-Z
tPD0
HIGH-Z
5
Doc. No. 25056-00 2/98 M-1
