CBTL03SB212
DisplayPort Gen2 sideband signal multiplexer
Rev. 1 — 21 February 2011
Product data sheet
1. General description
The CBTL03SB212 is a sideband signal multiplexer for DisplayPort Gen2 applications. It
provides one differential channel capable of switching or multiplexing (bidirectional and
AC-coupled) DisplayPort 1.2 Fast AUX or AUX signal, using high-bandwidth pass-gate
technology. Additionally, it provides for switching/multiplexing of the Hot Plug Detect signal
as well as the Display Data Channel (DDC) signals, for a total of three channels.
A typical application of CBTL03SB212 is on motherboards where one of two GPU display
sources needs to be selected to connect to a display sink device or connector. A controller
chip selects which path to use by setting a select signal HIGH or LOW. Due to the
non-directional nature of the signal paths (which use high-bandwidth pass-gate
technology), the CBTL03SB212 can also be used in the reverse topology, e.g., to connect
one display source device to one of two display sink devices or connectors.
GND
CBTL03SB212
AUX1+
AUX1−
AUX2+
AUX2−
+3.3 V
2:1
MUX
100 kΩ
AUX+
AUX−
100 kΩ
+3.3 V
GPU1
2 kΩ
DDC_CLK1
DDC_DAT1
DDC_CLK2
DDC_DAT2
HPD_1
HPD_2
2:1
MUX
HPD
2:1
MUX
DDC_CLK
DDC_DAT
SEL, XSD_N
GPU2
002aag007
Fig 1.
CBTL03SB212 application example
NXP Semiconductors
CBTL03SB212
DisplayPort Gen2 sideband signal multiplexer
2. Features and benefits
1 : 2 multiplexing of DisplayPort signals
1 high-speed differential channel for Fast AUX or AUX
1 channel for DDC clock and data
1 channel for HPD
High-bandwidth analog pass-gate technology
Very low intra-pair differential skew (5 ps typical)
Switch/MUX position select
Shutdown mode CMOS input
Shutdown mode minimizes power consumption while switching all channels off
Very low operation current of 0.2 mA typical
Very low shutdown current of < 10
μA
Single 3.3 V power supply
ESD 4 kV HBM, 1 kV CDM
Available in 4 mm
×
4 mm HVQFN20 package
3. Applications
Motherboard applications requiring DisplayPort sideband switching/multiplexing
Docking stations
Notebook computers
4. Ordering information
Table 1.
Ordering information
Package
Name
CBTL03SB212BS
HVQFN20
Description
plastic thermal enhanced very thin quad flat package; no leads;
20 terminals; body 4
×
4
×
0.85 mm
[1]
Version
SOT917-1
Type number
[1]
Total height after printed-circuit board mounting = 1 mm (maximum).
CBTL03SB212
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
2 of 16
NXP Semiconductors
CBTL03SB212
DisplayPort Gen2 sideband signal multiplexer
5. Functional diagram
AUX1+
AUX1−
AUX2+
AUX2−
2:1
MUX
AUX+
AUX−
DDC_CLK1
DDC_DAT1
DDC_CLK2
DDC_DAT2
2:1
MUX
DDC_CLK
DDC_DAT
HPD_1
2:1
MUX
HPD_2
HPD
SEL, XSD_N
002aag008
Fig 2.
Functional diagram
6. Pinning information
6.1 Pinning
17 AUX1+
16 AUX1−
15 XSD_N
14 AUX2+
13 AUX2−
12 DDC_CLK1
11 DDC_DAT1
HPD_1 10
6
7
8
DDC_DAT2
9
DDC_CLK2
20 AUX+
19 GND
HPD_2
terminal 1
index area
AUX−
DDC_CLK
DDC_DAT
HPD
SEL
1
2
3
4
5
CBTL03SB212BS
V
DD
18 V
DD
002aag009
Transparent top view
Fig 3.
Pin configuration for HVQFN20
CBTL03SB212
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
3 of 16
NXP Semiconductors
CBTL03SB212
DisplayPort Gen2 sideband signal multiplexer
6.2 Pin description
Table 2.
Symbol
SEL
XSD_N
Pin description
Pin
5
15
Type
3.3 V CMOS
single-ended input
3.3 V CMOS
single-ended input
Description
Selects between two multiplexer/switch paths.
Shutdown pin. Should be driven HIGH or
connected to V
DD
for normal operation. When
LOW, all paths are switched off (non-conducting
high-impedance state), and supply current
consumption is minimized.
High-speed differential pair for AUX signals,
right-side.
Pair of single-ended terminals for DDC clock and
data signals, right-side.
Single-ended channel for the HPD signal,
right-side.
High-speed differential pair for AUX signals, path 1,
left-side.
High-speed differential pair for AUX signals, path 2,
left-side.
Pair of single-ended terminals for DDC clock and
data signals, path 1, left-side.
Pair of single-ended terminals for DDC clock and
data signals, path 2, left-side.
Single-ended channel for the HPD signal, path 1,
left-side.
Single-ended channel for the HPD signal, path 2,
left-side.
3.3 V power supply.
Ground.
AUX+
AUX−
DDC_CLK
DDC_DAT
HPD
AUX1+
AUX1−
AUX2+
AUX2−
DDC_CLK1
DDC_DAT1
DDC_CLK2
DDC_DAT2
HPD_1
HPD_2
V
DD
GND
[1]
[1]
20
1
2
3
4
17
16
14
13
12
11
9
8
10
7
6, 18
19
differential I/O
differential I/O
differential I/O
differential I/O
single-ended I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
single-ended I/O
single-ended I/O
power supply
ground
HVQFN20 package die supply ground is connected to both GND pin and exposed center pad. GND pin and
the exposed center pad must be connected to supply ground for proper device operation. For enhanced
thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using
a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the printed-circuit board in the thermal pad region.
CBTL03SB212
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
4 of 16
NXP Semiconductors
CBTL03SB212
DisplayPort Gen2 sideband signal multiplexer
7. Functional description
Refer to
Figure 2 “Functional diagram”.
The CBTL03SB212 uses 3.3 V power supply. All signal paths are implemented using
high-bandwidth pass-gate technology, are bidirectional and no clock or reset signal is
needed for the multiplexer to function.
The switch position is selected using the select signal (SEL). The detailed operation is
described in
Section 7.1.
7.1 MUX select (SEL) function
The internal multiplexer switch position is controlled by the logic inputs SEL as described
below.
Table 3.
SEL
0
1
MUX select control
Path 2
high-impedance
active
Path 1
active
high-impedance
7.2 Shutdown function
The CBTL03SB212 provides a shutdown function to minimize power consumption when
the application is not active but power to the CBTL03SB212 is provided. Pin XSD_N
(active LOW) puts all channels in Off mode (non-conducting high-impedance state) while
reducing current consumption to near-zero.
Table 4.
XSD_N
0
1
Shutdown function
State
shutdown
active
CBTL03SB212
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
5 of 16
