D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate • Quad 2-Input NAND Buffered B Series Gate
October 1987
Revised January 1999
CD4001BC/CD4011BC
Quad 2-Input NOR Buffered B Series Gate •
Quad 2-Input NAND Buffered B Series Gate
General Description
The CD4001BC and CD4011BC quad gates are monolithic
complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement mode tran-
sistors. They have equal source and sink current
capabilities and conform to standard B series output drive.
The devices also have buffered outputs which improve
transfer characteristics by providing very high gain.
All inputs are protected against static discharge with diodes
to V
DD
and V
SS
.
Features
s
Low power TTL:
Fan out of 2 driving 74L compatibility:
s
5V–10V–15V parametric ratings
s
Symmetrical output characteristics
s
Maximum input leakage 1
µA
at 15V over full
temperature range
or 1 driving 74LS
Ordering Code:
Order Number
CD4001BCM
CD4001BCSJ
CD4001BCN
CD4011BCM
CD4011BCN
Package Number
M14A
M14D
N14A
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC and SOP
CD4001BC
Pin Assignments for DIP and SOIC
CD4011BC
Top View
Top View
© 1999 Fairchild Semiconductor Corporation
DS005939.prf
www.fairchildsemi.com
CD4001BC/CD4011BC
Schematic Diagrams
CD4001BC
1
/
4
of device shown
J
=
A
+
B
Logical “1”
=
HIGH
Logical “0”
=
LOW
All inputs protected by standard
CMOS protection circuit.
CD4011BC
1
/
4
of device shown
J
=
A•B
Logical “1”
=
HIGH
Logical “0”
=
LOW
All inputs protected by standard
CMOS protection circuit.
www.fairchildsemi.com
2
CD4001BC/CD4011BC
Absolute Maximum Ratings
(Note 1)
(Note 2)
Voltage at any Pin
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
V
DD
Range
Storage Temperature (T
S
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260°C
(Note 2)
700 mW
500 mW
−0.5
V
DC
to
+18
V
DC
−65°C
to
+150°C
−0.5V
to V
DD
+0.5V
Recommended Operating
Conditions
Operating Range (V
DD
)
Operating Temperature Range
CD4001BC, CD4011BC
−40°C
to
+85°C
Note 1:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The Electrical Characteristics tables provide conditions
for actual device operation.
Note 2:
All voltages measured with respect to V
SS
unless otherwise speci-
fied.
3 V
DC
to 15 V
DC
DC Electrical Characteristics
Symbol
I
DD
Parameter
Quiescent Device
Current
V
OL
LOW Level
Output Voltage
V
OH
HIGH Level
Output Voltage
V
IL
LOW Level
Input Voltage
V
IH
HIGH Level
Input Voltage
I
OL
LOW Level Output
Current
(Note 3)
I
OH
HIGH Level Output
Current
(Note 3)
I
IN
Input Current
Conditions
−40°C
Min
Max
1
2
4
0.05
0.05
0.05
4.95
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
0.52
1.3
3.6
−0.52
−1.3
−3.6
−0.30
0.30
3.5
7.0
11.0
0.44
1.1
3.0
−0.44
−1.1
−3.0
Min
+25°C
Typ
0.004
0.005
0.006
0
0
0
5
10
15
2
4
6
3
6
9
0.88
2.25
8.8
−0.88
−2.25
−8.8
−10
−5
+85°C
Max
1
2
4
0.05
0.05
0.05
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
0.36
0.9
2.4
−0.36
−0.9
−2.4
−0.30
0.30
−1.0
1.0
1.5
3.0
4.0
Min
Max
7.5
15
30
0.05
0.05
0.05
Units
µA
µA
µA
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
µA
µA
V
DD
=
5V, V
IN
=
V
DD
or V
SS
V
DD
=
10V, V
IN
=
V
DD
or V
SS
V
DD
=
15V, V
IN
=
V
DD
or V
SS
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V, V
O
=
4.5V
V
DD
=
10V, V
O
=
9.0V
V
DD
=
15V, V
O
=
13.5V
V
DD
=
5V, V
O
=
0.5V
V
DD
=
10V, V
O
=
1.0V
V
DD
=
15V, V
O
=
1.5V
V
DD
=
5V, V
O
=
0.4V
V
DD
=
10V, V
O
=
0.5V
V
DD
=
15V, V
O
=
1.5V
V
DD
=
5V, V
O
=
4.6V
V
DD
=
10V, V
O
=
9.5V
V
DD
=
15V, V
O
=
13.5V
V
DD
=
15V, V
IN
=
0V
V
DD
=
15V, V
IN
=
15V
|I
O
|
<
1
µA
9.95
14.95
|I
O
|
<
1
µA
10
−5
Note 3:
I
OL
and I
OH
are tested one output at a time.
AC Electrical Characteristics
Symbol
t
PHL
Parameter
Propagation Delay Time,
HIGH-to-LOW Level
t
PLH
Propagation Delay Time,
LOW-to-HIGH Level
t
THL
, t
TLH
Transition Time
(Note 4)
Conditions
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
Typ
120
50
35
110
50
35
90
50
40
5
14
Max
250
100
70
250
100
70
200
100
80
7.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
CD4001BC: T
A
=
25
°
C, Input t
r
; t
f
=
20 ns. C
L
=
50 pF, R
L
=
200k. Typical temperature coefficient is 0.3%/°C.
C
IN
C
PD
Average Input Capacitance
Power Dissipation Capacity
Any Input
Any Gate
Note 4:
AC Parameters are guaranteed by DC correlated testing.
3
www.fairchildsemi.com
CD4001BC/CD4011BC
AC Electrical Characteristics
Symbol
t
PHL
Parameter
Propagation Delay,
HIGH-to-LOW Level
t
PLH
Propagation Delay,
LOW-to-HIGH Level
t
THL
, t
TLH
Transition Time
(Note 5)
Conditions
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
Typ
120
50
35
85
40
30
90
50
40
5
14
Max
250
100
70
250
100
70
200
100
80
7.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
CD4011BC: T
A
=
25
°
C, Input t
r
; t
f
=
20 ns. C
L
=
50 pF, R
L
=
200k. Typical Temperature Coefficient is 0.3%/°C.
C
IN
C
PD
Average Input Capacitance
Power Dissipation Capacity
Any Input
Any Gate
Note 5:
AC Parameters are guaranteed by DC correlated testing.
Typical Performance Characteristics
Typical
Transfer Characteristics
Typical
Transfer Characteristics
Typical
Transfer Characteristics
www.fairchildsemi.com
4
