CD4015A Types
COS/MOS Dual 4-Stage Static Shift Register
With Serial Input/Parallel Output
The RCA-C04015A consists of two identical,
independent, 4-stage serial-input/parallel-
output registers_ Each register has indepen-
dent CLOCK and RESET inputs as well as
a single serial DATA input. "a" outputs are
available from each of the four stages on
both registers. All register stages are O·type,
master-slave flip-flops. The logic level pre·
sent at the DATA input is transferred into
the first register stage and shifted over one
stage at each positive-going clock transition.
Resetting of all stages is accomplished by a
high level on the reset line. Register expan·
sion to 8 stages using one C04015A package,
or to more than 8 stages using additional
C04015A's is possible.
These types are supplied in 16-lead her-
metic dual-in-line ceramic packages (0 and
F suffixes), 16-lead dual-in-line plastiC
packages (E suffix), 16-lead ceramic flat
packages (K suffix), and
In
chip form (H
suffix).
OArA.
0,.
0 ..
0 ..
0 ..
DATAl
.,.
0,.
0 ..
0 ..
CD4015A
FUNCTIONAL DIAGRAM
MAXIMUM RATINGS,
Absolute·Maximum Values:
STORAGE.TEMPERATURE RANGE (Tstgl . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150°C
OPERATING·TEMPERATURE RANGE (TA':
PACKAGE TYPES D. F, H
................................ ,
PACKAGE TYPE E
.......................•...•
.........
DC SUPPLY·VOL TAGE RANGE. (VDD'
(Voltages referenced to VSS Termlnall . . . . .
POWER DISSIPATION PER PACKAGE (PO'
FOR T A" -40 to + 60°C (PACKAGE TYPE E 1
FOR T A • +60 to +85°C (PACKAGE TYPE E I
FOR T A" -55 to + 100°C (PACKAGE TYPES D. Fl.
FOR TA • + 100 to +125°C (PACKAGE TYPES D. Fl
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A
c
Features:
• Medium speed operation ••......•...
5 MHz (typ.) dock rate at V DD
- VSS= 10V
•
•
Fully static operation
8 master-slave flip-flops
buffering
plus
output
-55 to +l25°C
-40 to +85°C
-0.5 to +15 V
..................... .
....
..............
500mW
500 mW
. . , . Derate Linearly at 12mWfC to 200 mW
. . . .Derate Llneerly et 12 mWfC to 200 mW
100 mW
FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES). . . .
. . . . . . . ..
INPUT VOLTAGE RANGE. ALL INPUTS. . . . . . ..
LEAD TEMPERATURE (DURING SOLDERINGI'
. . . . . . -0.5 to V DD +0.5 V
+265°C
• Quiescent current .pecified t
15 V
• Maximum input leakage current of 1 IlA
at 15 V (full package-temperature
range)
• 1-V noise margin (full package-tempera-
ture range)
e'
At distance
1/16
t
1/32
mch (1.59
±
079 mml from case for 10, max . . . . . . . . . . .
Applications:
• Serial·input!parallel-output data queueing
• Serial to parallel data conversion
• General-purpose register
TRUTH TABLE
RECOMMENDED OPERATING CONDITIONS
at TA
==
2~C,
Except as Noted.
For maximum reliability, nominal operating conditions should
be
Ii8lected so that
operation is always within the fol/owing ranges:
LIMITS
CHARACTERISTIC
VDD
(V)
D.F. H
PACKAGES
MIN.
Supply·Voltage Range (For T A
==
Full
Package-Temperature Range)
Data Setup Time, ts
5
10
5
10
5
10
5
10
5
10
3
350
80
500
175
dc
de
MAX.
12
E
PACKAGE
MIN.
3
500
100
830
200
de
de
MAX.
12
V
UNITS
Cl
A
0
R
0
0
0
01
0
an
°n-l
°n·1
an (N
0
../ 0
/1
,
'"""-
X
X
D
X
X
a,
0
o
CHANGE)
1
A.
LEVEL CHANGE
DON'T CARE CASE
Fig.
1 -
Truth rable.
-
-
Clock Pulse Width. tw
-
-
1
3
15
5
-
-
-
-
0.6
2.5
15
5
ns
ns
Clock Input Frequency. fCl
MHz
Clock Rise and Fall Time, trCl. tfCl·
-
-
-
-
830
200
IlS
Clock Reset Pulse Width. tw
500
175
-
-
-
-
ns
Fig.
2 -
TyplCllI clock Input frequtlncy
VI.
6upply voltllf/e.
-If more than one unit is cascadad trCL should be made less than or equal to the sum of the transition time
and the fixed propagation delay of the output of the driving stage for the estimatad capacitive load.
464 __________________________________________________________________
CD4015A Typ
s
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES 1°C)
CONDITIONS
CHARACTERISTICS
Vo
(V)
V
IN
V
DD
IV} (V)
0, F, H PACKAGES
-55
+25
E
PACKAGE
+25
UNITS
+85
TYP. LIMIT
+125
-40
50
100
500
TYP. LIMIT
QUiescent Device
Current. IL Max.
Output Voltage
Low Level,
VOL
High Level
VOH
NOISe Immunity
Inputs Low,
VNL
Inputs High
V NH
NOise Margan:
Inputs Low,
VNMl
Inputs High,
V NMH
Output Drove
Current·
N-<:hannel
(Sink/,
ION Min.
P·Channel
(Source).
'OP Min.
Input Leakage
Current,
IIL,IIH
-
-
-
-
-
-
-
-
5
10
15
5
5
10
50
05
1
1
5
10
50
300
600
2000
05
1
5
50
100
500
700
1400
5000
10
30
40
LOAO CAPACITANCE teL' -"
jJA
-
5
10
0
0
10
5
10
5
10
5
10
5
10
5
10
o
Typ.
0.05
Max
o
Typ.,
0.05
Max
V
495
Min.
5
Typ.
9.95
Man.;
10
Typ.
1 5
Min.
225
Typ
3
Min.,
4 5
Typ
V
-
42
9
0.8
1
4.5
9
0.5
1
Fig.
3. -
TVPiC81
propagation~elav
time
lIS.
load C8pacitBnce.
-
-
-
-
-
-
-
-
'"lo[NT ..
~
••
".'U".,
'.'
'z,-.:
I
1 5
Man .
225
Typ
3
Man
.4.5
Typ.
1
Man
1
Min.
1
Man
1
Mon
V
!1
600 I
!i:~0~:'
1~3
I~
:5 0'
·0 ,,.
.~
I~
I!
o
0.5
0.5
4.5
9.5
-
-
5
10
5
015
0.31
-0.1
0.3
05
012
0.25
0.085 0.072 0.3
0175
012
05
0.06
01
0.05
008
mA
Fig.
4 '-
TVpiC81 transition time
load C8pacitance.
lIS
-
-
-0.16 -008 -0055 -0.06 -016 -005 -004
044 -0.1
10 -0.25 -0.44 -0.20 -0.14 -0.12
ooa
00
0
.".NT T(WP(AATUR(
Any Input
n ...
I.2~·C
AtT(."AlIIriIG ·0·
:
~
-
1-1'5
tl0- 5
Typ.,
±1
Max
jJA
•
10'
""0 ",- PAn!A,.
I
f>
j
I-
10'
t
i
~
10'
~= ~
......
~-ITtb\· .~~
.....
·Rt
JLk--
,..
!
!
'
;..-
~.
i .,
"
D.
a
K)'
.....
-
H
.
--
----Cl·~p'
LOAD C.tJ!IACITAJfC( ItL)"''''
-nTr,1IT
*
Fig.
5 -
Tvpical diuiPBt!On character/.tiel.
CL,
"
*
*
ALL INPUTS ARE
_
£\
'00
~
Ct.
Vss
~
PROTECTED
BY
COSI
MOS PROTEC TION
NETWORK
Fig.
6 -
Logic diagram.
_______________________________________________________________________ 465
CD4015A Typ
s
DYNAMIC ELECTRICAL CHARACTERISTICS
st TA
co
25"C, Input tr , tf
=
20 ns, CL
=
15
pF, R L
=
200
kn
INPUTQVOO
OUTPUTS
VOo-t..-
CHARACTERISTIC
TEST
CONDITIONS
LIMITS
D. F, H
PACKAGES
MIN.
E
PACKAGE
UNITS
o
VNL
~
_
rF
(VI
CLOCKED OPERATION
Propagation Delay
Time;
TplH,TpHl
Transition Time;
tTHl' tTlH
Minimum Clock Pulse
Width,
NOT[
VSS
TYP. MAX. MIN. TYP. MAX.
:':"N~NU~~_'NAT'ON
Fig.
7 -
NoiStl-immuniry tII,t circuit,
5
10
5
10
5
10
5
10
5
10
5
10
-
-
300
100
150
75
200
100
750
225
300
125
500
175
15
5
350
80
tw
-
-
-
-
Clock Rise
&
Fall
Time; trCl, tfCl·
Minimum Data Set-
upTime, ts
Maximum Clock
Input Frequency,
fCl
Average Input
Capacitance, C,
RESET OPERATION
Propagation Delay
Time, TpHl
Minimum/
Reset Pulse Width
-
-
-
-
1
3
-
-
-
100
50
2.5
5
5
-
-
-
-
-
-
-
-
-
300 1000
100 300
150
75
200
100
400
150
830
200
15
5
500
100
-
ns
ns
ns
V~NPU(J'
::::"M
"~
o
~
Vss
VSS
"M'
-
S[OU[NTIALLY.
TO BOT H Voo
ANI)
VSS
CONNECT ALL
UHUSm
INPUTS TO EITHER
Voo OR VSS
-
100
50
2.5
5
5
/.LS
-
0.6
2.5
ns
Fig.
8 -
Input-leakage-current tIIlt
circuit.
-
-
-
750
225
500
175
-
MHz
-
-
-
-
-
-
pF
5
10
5
10
Vi
-
-
-
-
300
100
200
100
300 1000
100 300
200
100
830
200
ns
ns
\
·If
more then one unit is C8Scaded trCL should
be
mede less than or equal to the sum of the transition time and
the fixed propagation delay of the output of the driving stage for the estimated capacitve load.
Test performed with the following
sequence of ",'," and "0',"
Test
Test
Test
Test
Test
Test
Test
Don't Test
Test
10V
Don't
Don't
Don't
Don't
Don't
S,
0
0
0
0
0
S2
CO
,
,
,
S3
0
TERMINAL DIAGRAM
Top View
CLOCK
e
04
e
03A
02A
01 A
RESET A
DATA A
I.
2
3
"'
o
o
o
o
o
o
o
,
0
0
16
15
Voo
DATA
e
RES[T B
01 B
02B
03B
04A
CLOCK A
92CS·244~1
,
0
0
13
12
II
vss
10
9
Fig.
9 -
QuiesCflnt~e"iCfl-current
tl18t circuit.
466 ______________________________________________________________________
