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CD4053BCN_NL

Single-Ended Multiplexer, 3 Func, 2 Channel, CMOS, PDIP16, 0.300 INCH, PLASTIC, MS-001, DIP-16

器件类别:模拟混合信号IC    信号电路   

厂商名称:Fairchild

厂商官网:http://www.fairchildsemi.com/

器件标准:

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器件参数
参数名称
属性值
是否Rohs认证
符合
厂商名称
Fairchild
零件包装代码
DIP
包装说明
0.300 INCH, PLASTIC, MS-001, DIP-16
针数
16
Reach Compliance Code
compliant
模拟集成电路 - 其他类型
SINGLE-ENDED MULTIPLEXER
JESD-30 代码
R-PDIP-T16
JESD-609代码
e3
长度
19.305 mm
负电源电压最大值(Vsup)
负电源电压最小值(Vsup)
标称负供电电压 (Vsup)
信道数量
2
功能数量
3
端子数量
16
通态电阻匹配规范
10 Ω
最大通态电阻 (Ron)
1050 Ω
最高工作温度
125 °C
最低工作温度
-55 °C
封装主体材料
PLASTIC/EPOXY
封装代码
DIP
封装等效代码
DIP16,.3
封装形状
RECTANGULAR
封装形式
IN-LINE
峰值回流温度(摄氏度)
NOT APPLICABLE
电源
5/15 V
认证状态
Not Qualified
座面最大高度
5.08 mm
最大供电电压 (Vsup)
15 V
最小供电电压 (Vsup)
5 V
标称供电电压 (Vsup)
5 V
表面贴装
NO
最长断开时间
420 ns
最长接通时间
1200 ns
切换
BREAK-BEFORE-MAKE
技术
CMOS
温度等级
MILITARY
端子面层
Matte Tin (Sn)
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT APPLICABLE
宽度
7.62 mm
Base Number Matches
1
文档预览
CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer • Dual 4-Channel Analog
Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer
November 1983
Revised April 2002
CD4051BC • CD4052BC • CD4053BC
Single 8-Channel Analog Multiplexer/Demultiplexer •
Dual 4-Channel Analog Multiplexer/Demultiplexer •
Triple 2-Channel Analog Multiplexer/Demultiplexer
General Description
The CD4051BC, CD4052BC, and CD4053BC analog mul-
tiplexers/demultiplexers are digitally controlled analog
switches having low “ON” impedance and very low “OFF”
leakage currents. Control of analog signals up to 15V
p-p
can be achieved by digital signal amplitudes of 3
15V. For
example, if V
DD
=
5V, V
SS
=
0V and V
EE
= −
5V, analog sig-
nals from
5V to
+
5V can be controlled by digital inputs of
0
5V. The multiplexer circuits dissipate extremely low qui-
escent power over the full V
DD
V
SS
and V
DD
V
EE
supply
voltage ranges, independent of the logic state of the control
signals. When a logical “1” is present at the inhibit input ter-
minal all channels are “OFF”.
CD4051BC is a single 8-channel multiplexer having three
binary control inputs. A, B, and C, and an inhibit input. The
three binary signals select 1 of 8 channels to be turned
“ON” and connect the input to the output.
CD4052BC is a differential 4-channel multiplexer having
two binary control inputs, A and B, and an inhibit input. The
two binary input signals select 1 or 4 pairs of channels to
be turned on and connect the differential analog inputs to
the differential outputs.
CD4053BC is a triple 2-channel multiplexer having three
separate digital control inputs, A, B, and C, and an inhibit
input. Each control input selects one of a pair of channels
which are connected in a single-pole double-throw configu-
ration.
Features
s
Wide range of digital and analog signal levels:
digital 3 – 15V, analog to 15V
p-p
s
Low “ON” resistance: 80
(typ.) over entire 15V
p-p
signal-input range for V
DD
V
EE
=
15V
s
High “OFF” resistance:
channel leakage of
±
10 pA (typ.) at V
DD
V
EE
=
10V
s
Logic level conversion for digital addressing signals of
3 – 15V (V
DD
V
SS
=
3 – 15V) to switch analog signals
to 15 V
p-p
(V
DD
V
EE
=
15V)
s
Matched switch characteristics:
R
ON
=
5
(typ.) for V
DD
V
EE
=
15V
s
Very low quiescent power dissipation under all
digital-control input and supply conditions:
1
µ
W (typ.) at V
DD
V
SS
=
V
DD
V
EE
=
10V
s
Binary address decoding on chip
Ordering Code:
Order Number
CD4051BCM
CD4051BCSJ
CD4051BCMTC
CD4051BCN
CD4052BCM
CD4052BCSJ
CD4052BCN
CD4053BCM
CD4053BCSJ
CD4053BCN
Package Number
M16A
M16D
MTC16
N16E
M16A
M16D
N16E
M16A
M16D
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2002 Fairchild Semiconductor Corporation
DS005662
www.fairchildsemi.com
CD4051BC • CD4052BC • CD4053BC
Connection Diagrams
Pin Assignments for DIP and SOIC
CD4051BC
CD4052BC
CD4053BC
Truth Table
INPUT STATES
INHIBIT
0
0
0
0
0
0
0
0
1
*Don’t Care condition.
“ON” CHANNELS
A
0
1
0
1
0
1
0
1
*
CD4051B
0
1
2
3
4
5
6
7
NONE
NONE
CD4052B
0X, 0Y
1X, 1Y
2X, 2Y
3X, 3Y
CD4053B
cx, bx, ax
cx, bx, ay
cx, by, ax
cx, by, ay
cy, bx, ax
cy, bx, ay
cy, by, ax
cy, by, ay
NONE
C
0
0
0
0
1
1
1
1
*
B
0
0
1
1
0
0
1
1
*
www.fairchildsemi.com
2
CD4051BC • CD4052BC • CD4053BC
Logic Diagrams
CD4051BC
CD4052BC
3
www.fairchildsemi.com
CD4051BC • CD4052BC • CD4053BC
Logic Diagrams
(Continued)
CD4053BC
www.fairchildsemi.com
4
CD4051BC • CD4052BC • CD4053BC
Absolute Maximum Ratings
(Note 1)
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Storage Temperature
Range (T
S
)
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Lead Temperature (T
L
)
(soldering, 10 seconds)
260
°
C
(Note 2)
700 mW
500 mW
0.5 V
DC
to
+
18 V
DC
0.5 V
DC
to V
DD
+
0.5 V
DC
65
°
C to
+
150
°
C
Recommended Operating
Conditions
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Operating Temperature Range (T
A
)
CD4051BC/CD4052BC/CD4053BC
+
5 V
DC
to
+
15 V
DC
0V to V
DD
V
DC
55
°
C to
+
125
°
C
Note 1:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The Electrical Characteristics tables provide conditions
for actual device operation.
DC Electrical Characteristics
Symbol
Parameter
Control A, B, C and Inhibit
I
IN
Input Current
V
DD
=
15V,
V
IN
=
0V
V
DD
=
15V,
V
IN
=
15V
I
DD
Quiescent Device Current
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
Signal Inputs (V
IS
) and Outputs (V
OS
)
R
ON
“ON” Resistance (Peak
for V
EE
V
IS
V
DD
)
R
L
=
10 kΩ
(any channel
selected)
Conditions
−55°C
Min
Max
Min
+25°
Typ
Max
−0.1
125°C
Min
Max
Units
V
EE
=
0V
V
EE
=
0V
−0.1
0.1
5
10
20
−10
5
10
5
−1.0
µA
1.0
150
300
600
µA
0.1
5
10
20
V
DD
=
2.5V,
V
EE
= −2.5V
or V
DD
=
5V,
V
EE
=
0V
V
DD
=
5V,
V
EE
= −5V
or V
DD
=
10V,
V
EE
=
0V
V
DD
=
7.5V,
V
EE
= −7.5V
or V
DD
=
15V,
V
EE
=
0V
200
80
240
320
310
120
400
550
800
270
1050
1300
∆R
ON
“ON” Resistance
Between Any Two
Channels
R
L
=
10 kΩ
(any channel
selected)
V
DD
=
2.5V,
V
EE
= −2.5V
or V
DD
=
5V,
V
EE
=
0V
V
DD
=
5V
V
EE
= −5V
or V
DD
=
10V,
V
EE
=
0V
V
DD
=
7.5V,
V
EE
= −7.5V
or V
DD
=
15V,
V
EE
=
0V
5
10
10
“OFF” Channel Leakage
“OFF” Channel Leakage
Current, all channels
“OFF” (Common
OUT/IN)
V
DD
=7.5V,
Inhibit
=
7.5V
V
DD
=
7.5V,
V
EE
= −7.5V,
O/I
=
0V
I/O
= ±7.5V
V
EE
=−7.5V
±50
±200
±200
±200
±0.01
±0.08
±0.04
±0.02
±50
±200
±200
±200
±500
±2000
±2000
±2000
nA
nA
CD4051
D4052
CD4053
Current, any channel “OFF” O/I=±7.5V, I/O=0V
5
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参数对比
与CD4053BCN_NL相近的元器件有:CD4053BCSJX_NL、CD4051BCSJX_NL、CD4052BCSJX_NL、CD4052BCN_NL。描述及对比如下:
型号 CD4053BCN_NL CD4053BCSJX_NL CD4051BCSJX_NL CD4052BCSJX_NL CD4052BCN_NL
描述 Single-Ended Multiplexer, 3 Func, 2 Channel, CMOS, PDIP16, 0.300 INCH, PLASTIC, MS-001, DIP-16 Single-Ended Multiplexer, 3 Func, 2 Channel, CMOS, PDSO16, 5.30 MM, EIAJ TYPE2, SOP-16 Single-Ended Multiplexer, 1 Func, 8 Channel, CMOS, PDSO16, Differential Multiplexer, 1 Func, 4 Channel, CMOS, PDSO16, 5.30 MM, EIAJ TYPE2, SOP-16 Differential Multiplexer, 1 Func, 4 Channel, CMOS, PDIP16, 0.300 INCH, PLASTIC, MS-001, DIP-16
是否Rohs认证 符合 符合 符合 符合 符合
包装说明 0.300 INCH, PLASTIC, MS-001, DIP-16 5.30 MM, EIAJ TYPE2, SOP-16 SOP, SOP16,.3 SOP, SOP16,.3 DIP, DIP16,.3
Reach Compliance Code compliant compliant compliant compliant compliant
模拟集成电路 - 其他类型 SINGLE-ENDED MULTIPLEXER SINGLE-ENDED MULTIPLEXER SINGLE-ENDED MULTIPLEXER DIFFERENTIAL MULTIPLEXER DIFFERENTIAL MULTIPLEXER
JESD-30 代码 R-PDIP-T16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDIP-T16
信道数量 2 2 8 4 4
功能数量 3 3 1 1 1
端子数量 16 16 16 16 16
最大通态电阻 (Ron) 1050 Ω 1050 Ω 1200 Ω 1050 Ω 1050 Ω
最高工作温度 125 °C 125 °C 85 °C 125 °C 125 °C
最低工作温度 -55 °C -55 °C -40 °C -55 °C -55 °C
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 DIP SOP SOP SOP DIP
封装等效代码 DIP16,.3 SOP16,.3 SOP16,.3 SOP16,.3 DIP16,.3
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 IN-LINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE IN-LINE
电源 5/15 V 5/15 V 5/15 V 5/15 V 5/15 V
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
表面贴装 NO YES YES YES NO
切换 BREAK-BEFORE-MAKE BREAK-BEFORE-MAKE BREAK-BEFORE-MAKE BREAK-BEFORE-MAKE BREAK-BEFORE-MAKE
技术 CMOS CMOS CMOS CMOS CMOS
温度等级 MILITARY MILITARY INDUSTRIAL MILITARY MILITARY
端子形式 THROUGH-HOLE GULL WING GULL WING GULL WING THROUGH-HOLE
端子节距 2.54 mm 1.27 mm 1.27 mm 1.27 mm 2.54 mm
端子位置 DUAL DUAL DUAL DUAL DUAL
厂商名称 Fairchild Fairchild - Fairchild Fairchild
零件包装代码 DIP SOIC - SOIC DIP
针数 16 16 - 16 16
JESD-609代码 e3 e3 - e3 e3
长度 19.305 mm 10.2 mm - 10.2 mm 19.305 mm
通态电阻匹配规范 10 Ω 10 Ω - 10 Ω 10 Ω
峰值回流温度(摄氏度) NOT APPLICABLE 260 - 260 NOT APPLICABLE
座面最大高度 5.08 mm 2.1 mm - 2.1 mm 5.08 mm
最大供电电压 (Vsup) 15 V 15 V - 15 V 15 V
最小供电电压 (Vsup) 5 V 5 V - 5 V 5 V
标称供电电压 (Vsup) 5 V 5 V - 5 V 5 V
最长断开时间 420 ns 420 ns - 420 ns 420 ns
最长接通时间 1200 ns 1200 ns - 1200 ns 1200 ns
端子面层 Matte Tin (Sn) Matte Tin (Sn) - Matte Tin (Sn) Matte Tin (Sn)
处于峰值回流温度下的最长时间 NOT APPLICABLE NOT SPECIFIED - NOT SPECIFIED NOT APPLICABLE
宽度 7.62 mm 5.3 mm - 5.3 mm 7.62 mm
Base Number Matches 1 1 1 - -
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