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CD4504BT
Functional Diagram
V
DD
V
CC
V
DD
LEVEL
SHIFTER
OUT
(2, 4, 6, 10, 12, 15)
†
IN
(3, 5, 7, 9, 11, 14)
†
ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
SELECT
†
13
V
SS
TTL/CMOS
MODE SELECT
V
CC
= PIN 1
V
DD
= PIN 16
V
SS
= PIN 8
2
CD4504BT
Die Characteristics
DIE DIMENSIONS:
(2540µm x 1753µm x 533µm
±25.4µm)
100 x 69 x 21mils
±1mil
METALLIZATION:
Type: Al
Thickness: 12.5k
Å
±1.5k
Å
SUBSTRATE POTENTIAL:
Leave Floating or Tie to V
DD
Bond Pad #16 (V
DD
) First
BACKSIDE FINISH:
Silicon
PASSIVATION:
Type: Phosphorus Doped Silox (S
i
O
2
)
Thickness: 13.0k
Å
±2.6k
Å
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm
2
TRANSISTOR COUNT:
72
PROCESS:
Bulk CMOS
Metallization Mask Layout
CD4504BT
69mils
100mils
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ISO9000
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