CD4514BC • CD4515BC 4-Bit Latched/4-to-16 Line Decoders
October 1987
Revised January 2004
CD4514BC • CD4515BC
4-Bit Latched/4-to-16 Line Decoders
General Description
The CD4514BC and CD4515BC are 4-to-16 line decoders
with latched inputs implemented with complementary MOS
(CMOS) circuits constructed with N- and P-channel
enhancement mode transistors. These circuits are prima-
rily used in decoding applications where low power dissipa-
tion and/or high noise immunity is required.
The CD4514BC (output active high option) presents a logi-
cal “1” at the selected output, whereas the CD4515BC pre-
sents a logical “0” at the selected output. The input latches
are R–S type flip-flops, which hold the last input data pre-
sented prior to the strobe transition from “1” to “0”. This
input data is decoded and the corresponding output is acti-
vated. An output inhibit line is also available.
Features
s
Wide supply voltage range:
s
Low power TTL: fan out of 2
compatibility:
driving 74L
s
Low quiescent power dissipation:
0.025
µ
W/package @ 5.0 V
DC
s
Single supply operation
s
Input impedance
=
10
12
Ω
typically
s
Plug-in replacement for MC14514, MC14515
3.0V to 15V
s
High noise immunity: 0.45 V
DD
(typ.)
Ordering Code:
Order Number
CD4514BCWM
CD4514BCN
CD4515BCWM
(Note 1)
CD4515BCN
Package Number
M24B
N24A
M24B
N24A
Package Diagram
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide
Note 1:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Top View
© 2004 Fairchild Semiconductor Corporation
DS005994
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CD4514BC • CD4515BC
Truth Table
Decode Truth Table (Strobe
=
1)
Data Inputs
Inhibit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
=
Don’t Care
Selected Output
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
CD4514
=
Logic “1”
CD4515
=
Logic “0”
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
All Outputs
=
0, CD4514
All Outputs
=
1, CD4515
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
Logic Diagram
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2
CD4514BC • CD4515BC
Absolute Maximum Ratings
(Note 2)
(Note 3)
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Storage Temperature Range (T
S
)
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
°
C
700 mW
500 mW
Recommended Operating
Conditions
(Note 3)
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Operating Temperature Range (T
A
)
CD4514BC, CD4515BC
3V to 15V
0V to V
DD
−
0.5V to
+
18V
−
0.5V to V
DD
+
0.5V
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
Note 2:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The tables of “Recommended Operating Conditions”
and “Electrical Characteristics” provide conditions for actual device opera-
tion.
Note 3:
V
SS
=
0V unless otherwise specified.
DC Electrical Characteristics
(Note 3)
CD4514BC, CD4515BC
Symbol
I
DD
Parameter
Quiescent Device
Current
V
OL
LOW Level
Output Voltage
Conditions
V
DD
=
5V, V
IN
=
V
DD
or V
SS
V
DD
=
10V, V
IN
=
V
DD
or V
SS
V
DD
=
15V, V
IN
=
V
DD
or V
SS
V
IL
=
0V, V
IH
=
V
DD
,
|I
O
|
<
1
µA
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
OH
HIGH Level
Output Voltage
V
IL
=
0V, V
IH
=
V
DD
,
|I
O
|
<
1
µA
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
IL
LOW Level
Input Voltage
|I
O
|
<
1
µA
V
DD
=
5V, V
O
=
0.5V or 4.5V
V
DD
=
10V, V
O
=
1.0V or 9.0V
V
DD
=
15V, V
O
=
1.5V or 13.5V
V
IH
HIGH Level
Input Voltage
|I
O
|
<
1
µA
V
DD
=
5V, V
O
=
0.5V or 4.5V
V
DD
=
10V, V
O
=
1.0V or 9.0V
V
DD
=
15V, V
O
=
1.5V or 13.5V
I
OL
LOW Level Output
Current (Note 4)
I
OH
HIGH Level Output
Current (Note 4)
I
IN
Input Current
V
DD
=
5V, V
O
=
0.4V
V
DD
=
10V, V
O
=
0.5V
V
DD
=
15V, V
O
=
1.5V
V
DD
=
5V, V
O
=
4.6V
V
DD
=
10V, V
O
=
9.5V
V
DD
=
15V, V
O
=
13.5V
V
DD
=
15V, V
IN
=
0V
V
DD
=
15V, V
IN
=
15V
Note 4:
I
OH
and I
OL
are tested one output at a time.
−55°C
Min
Max
5
10
20
Min
+25°C
Typ
0.005
0.010
0.015
Max
5
10
20
+125°C
Min
Max
150
300
600
Units
µA
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
0.64
1.6
4.2
−0.64
−1.6
−4.2
−0.1
0.1
4.95
9.95
14.95
5.0
10.0
15.0
2.25
4.50
6.75
1.5
3.0
4.0
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
0.36
0.90
2.4
−0.36
−0.90
−2.4
−0.1
0.1
−1.0
1.0
µA
mA
mA
V
V
V
3.5
7.0
11.0
0.51
1.3
3.4
−0.51
−1.3
−3.4
2.75
5.50
8.25
0.88
2.25
8.8
−0.88
−2.25
−8.8
−10
−
5
10
−
5
3
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CD4514BC • CD4515BC
AC Electrical Characteristics
t
THL
, t
TLH
Transition Times
(Note 5)
Min
Typ
100
50
40
550
225
150
400
150
100
125
50
38
175
50
38
150
5
7.5
Max
200
100
80
1100
450
300
800
300
200
250
100
75
350
100
75
pF
pF
ns
ns
ns
ns
ns
Units
All types C
L
=
50 pF, T
A
=
25
°
C, t
r
=
t
f
=
20 ns unless otherwise specified
Symbol
Parameter
Conditions
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
t
PLH
, t
PHL
Propagation Delay Times
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
t
PLH
, t
PHL
Inhibit Propagation
Delay Times
t
SU
Setup Time
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
t
WH
Strobe Pulse Width
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
C
PD
C
IN
Power Dissipation Capacitance
Input Capacitance
Per Package (Note 6)
Any Input (Note 7)
Note 5:
AC Parameters are guaranteed by DC correlated testing.
Note 6:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note,
AN-90.
Note 7:
Capacitance is guaranteed by periodic testing.
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4
CD4514BC • CD4515BC
AC Test Circuit and Switching Time Waveforms
FIGURE 1.
5
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