1:8 DMUX FOLLOWED BY LATCH; RESET ACTIVE ONLY WHEN LATCH ENABLE IS HIGH
系列
4000/14000/40000
JESD-30 代码
R-PDIP-T16
JESD-609代码
e0
长度
19.305 mm
负载电容（CL）
50 pF
逻辑集成电路类型
D LATCH
位数
1
功能数量
1
端子数量
16
最高工作温度
125 °C
最低工作温度
-55 °C
输出极性
TRUE
封装主体材料
PLASTIC/EPOXY
封装代码
DIP
封装等效代码
DIP16,.3
封装形状
RECTANGULAR
封装形式
IN-LINE
峰值回流温度（摄氏度）
NOT SPECIFIED
电源
3/15 V
Prop。Delay @ Nom-Su
400 ns
传播延迟（tpd）
400 ns
认证状态
Not Qualified
座面最大高度
5.08 mm
最大供电电压 (Vsup)
15 V
最小供电电压 (Vsup)
3 V
标称供电电压 (Vsup)
5 V
表面贴装
NO
技术
CMOS
温度等级
MILITARY
端子面层
Tin/Lead (Sn/Pb)
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
触发器类型
LOW LEVEL
宽度
7.62 mm
文档预览
CD4723BM CD4723BC Dual 4-Bit Addressable Latch
CD4724BM CD4724BC 8-Bit Addressable Latch
February 1988
CD4723BM CD4723BC Dual 4-Bit Addressable Latch
CD4724BM CD4724BC 8-Bit Addressable Latch
General Description
The CD4723B is a dual 4-bit addressable latch with com-
mon control inputs including two address inputs (A0 A1)
an active low enable input (E) and an active high clear input
(CL) Each latch has a data input (D) and four outputs (Q0 –
Q3) The CD4724B is an 8-bit addressable latch with three
address inputs (A0–A2) an active low enable input (E) ac-
tive high clear input (CL) a data input (D) and eight outputs
(Q0–Q7)
Data is entered into a particular bit in the latch when that is
addressed by the address inputs and the enable (E) is low
Data entry is inhibited when enable (E) is high
When clear (CL) and enable (E) are high all outputs are low
When clear (CL) is high and enable (E) is low the channel
demultiplexing occurs The bit that is addressed has an ac-
tive output which follows the data input while all unad-
dressed bits are held low When operating in the address-
able latch mode (E
e
CL
e
low) changing more than one
bit of the address could impose a transient wrong address
Therefore this should only be done while in the memory
mode (E
e
high CL
e
low)
Features
Y
Y
Y
Y
Y
Y
Y
Y
Wide supply voltage range
3 0V to 15V
High noise immunity
0 45 V
DD
(typ )
Low power TTL
fan out of 2 driving 74L
compatibility
or 1 driving 74LS
Serial to parallel capability
Storage register capability
Random (addressable) data entry
Active high demultiplexing capability
Common active high clear
Connection Diagrams
CD4723B
Dual-In-Line Package
CD4724B
Dual-In-Line Package
Order Number CD4723B or
CD4724B
TL F 6003–1
TL F 6003 – 2
Top View
Top View
Truth Table
Mode Selection
E
L
H
L
H
CL
L
L
H
H
Addressed
Latch
Follows Data
Hold Previous Data
Follows Data
Reset to ‘0’’
Unaddressed
Latch
Holds Previous Data
Holds Previous Data
Reset to ‘‘0’’
Reset to ‘‘0’’
Mode
Addressable Latch
Memory
Demultiplexer
Clear
C
1995 National Semiconductor Corporation
TL F 6003
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Notes 1
2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Storage Temperature (T
S
)
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Lead Temperature (T
L
)
(Soldering 10 seconds)
b
0 5V to
a
18 V
DC
b
0 5V to V
DD
a
0 5 V
DC
b
65 C to
a
150 C
Recommended Operating
Conditions
(Note 2)
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Operating Temperature Range (T
A
)
CD4723BM CD4724BM
CD4723BC CD4724BC
3 0V to 15 V
DC
0V to V
DD
V
DC
b
55 C to
a
125 C
b
40 C to
a
85 C
700 mW
500 mW
260 C
CD4724BM (Note 2)
b
55 C
a
25 C
a
125 C
DC Electrical Characteristics
CD4723BM
Symbol
I
DD
Parameter
Quiescent Device
Current
Low Level
Output Voltage
Conditions
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
Units
mA
mA
mA
V
V
V
V
V
V
Min
Max
50
10
20
0 05
0 05
0 05
Min
Typ
0 02
0 02
0 02
0
0
0
Max
50
10
20
0 05
0 05
0 05
Min
Max
150
300
600
0 05
0 05
0 05
V
OL
l
I
O
l
s
1
mA
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
OH
High Level
Output Voltage
l
I
O
l
s
1
mA
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V V
O
e
0 5V or 4 5V
V
DD
e
10V V
O
e
1V or 9V
V
DD
e
15V V
O
e
1 5V or 13 5V
V
DD
e
5V V
O
e
0 5V or 4 5V
V
DD
e
10V V
O
e
1V or 9V
V
DD
e
15V V
O
e
1 5V or 13 5V
V
DD
e
5V V
O
e
0 4V
V
DD
e
10V V
O
e
0 5V
V
DD
e
15V V
O
e
1 5V
V
DD
e
5V V
O
e
4 6V
V
DD
e
10V V
O
e
9 5V
V
DD
e
15V V
O
e
13 5V
V
DD
e
15V V
IN
e
0V
V
DD
e
15V V
IN
e
15V
4 95
9 95
14 95
15
30
40
35
70
11 0
0 64
16
42
b
0 64
b
1 6
b
4 2
b
0 1
4 95
9 95
14 95
50
10
15
2 25
45
6 75
15
30
40
4 95
9 95
14 95
15
30
40
35
70
11 0
0 36
09
24
b
0 36
b
0 9
b
2 4
b
0 1
b
1 0
V
IL
Low Level
Input Voltage
High Level
Input Voltage
Low Level Output
Current
(Note 3)
High Level Output
Current
(Note 3)
Input Current
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
V
IH
35
70
11 0
0 51
13
34
b
0 51
b
1 3
b
3 4
2 75
55
8 25
0 88
2 25
88
b
0 88
b
2 25
b
8 8
b
10
b
5
I
OL
I
OH
I
IN
01
10
b
5
01
10
mA
mA
Note 1
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices
should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and Electrical Characteristics’’ provide conditions for actual device
operation
Note 2
V
SS
e
0V unless otherwise specified
Note 3
I
OL
and I
OH
are tested one output at a time
2
DC Electrical Characteristics
CD4723BC
Symbol
I
DD
Parameter
Quiescent Device
Current
Low Level
Output Voltage
Conditions
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
CD4724BC (Note 2)
b
40 C
a
25 C
a
85 C
Units
mA
mA
mA
V
V
V
V
V
V
Min
Max
20
40
80
0 05
0 05
0 05
Min
Typ
0 02
0 02
0 02
0
0
0
Max
20
40
80
0 05
0 05
0 05
Min
Max
150
300
600
0 05
0 05
0 05
V
OL
l
I
O
l
s
1
mA
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
OH
High Level
Output Voltage
l
I
O
l
s
1
mA
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V V
O
e
0 5V or 4 5V
V
DD
e
10V V
O
e
1V or 9V
V
DD
e
15V V
O
e
1 5V or 13 5V
V
DD
e
5V V
O
e
0 5V or 4 5V
V
DD
e
10V V
O
e
1V or 9V
V
DD
e
15V V
O
e
1 5V or 13 5V
V
DD
e
5V V
O
e
0 4V
V
DD
e
10V V
O
e
0 5V
V
DD
e
15V V
O
e
1 5V
4 95
9 95
14 95
15
30
40
35
70
11 0
0 52
13
36
b
0 52
b
1 3
b
3 6
b
0 30
4 95
9 95
14 95
50
10
15
2 25
45
6 75
15
30
40
4 95
9 95
14 95
15
30
40
35
70
11 0
0 36
09
24
b
0 36
b
0 9
b
2 4
b
0 30
b
1 0
V
IL
Low Level
Input Voltage
High Level
Input Voltage
Low Level Output
Current
(Note 3)
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
V
IH
35
70
11 0
0 44
11
30
b
0 44
b
1 1
b
3 0
2 75
55
8 25
0 88
2 25
88
b
0 88
b
2 25
b
8 8
b
10
b
5
I
OL
I
OH
High Level Output V
DD
e
5V V
O
e
4 6V
Current
V
DD
e
10V V
O
e
9 5V
(Note 3)
V
DD
e
15V V
O
e
13 5V
Input Current
V
DD
e
15V V
IN
e
0V
V
DD
e
15V V
IN
e
15V
I
IN
0 30
10
b
5
0 30
10
mA
mA
Note 1
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices
should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and Electrical Characteristics’’ provide conditions for actual device
operation
Note 2
V
SS
e
0V unless otherwise specified
Note 3
I
OL
and I
OH
are tested one output at a time
3
AC Electrical Characteristics
T
A
e
25 C C
L
e
50 pF R
L
e
200k Input t
r
e
t
f
e
20 ns unless otherwise noted
Symbol
t
PHL tPLH
Parameter
Propagation Delay
Data to Output
Propagation Delay
Enable to Output
Propagation Delay
Clear to Output
Propagation Delay
Address to Output
Transition Time
(Any Output)
Minimum Data
Pulse Width
Minimum Address
Pulse Width
Minimum Clear
Pulse Width
Minimum Setup Time
Data to E
Minimum Hold Time
Data to E
Minimum Setup Time
Address to E
Minimum Hold Time
Address to E
Power Dissipation
Capacitance
Input Capacitance
Conditions
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
Per Package
(Note 4)
Any Input
Min
Typ
200
75
50
200
80
60
175
80
65
225
100
75
100
50
40
100
50
40
200
100
65
75
40
25
40
20
15
60
30
25
b
15
Max
400
150
100
400
160
120
350
160
130
450
200
150
200
100
80
200
100
80
400
200
125
150
75
50
80
40
30
120
60
50
50
30
20
15
10
5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
t
PLH
t
PHL
t
PHL
t
PLH
t
PHL
t
THL
t
TLH
T
WH
T
WL
t
WH
t
WL
t
WH
t
SU
t
H
t
SU
0
0
b
50
b
20
b
15
t
H
C
PD
C
IN
100
50
75
pF
AC Parameters are guaranteed by DC correlated testing
Note 1
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices
should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and Electrical Characteristics’’ provide conditions for actual device
operation
Note 2
V
SS
e
0V unless otherwise specified
Note 3
I
OL
and I
OH
are tested one output at a time
Note 4
Dynamic power dissipation (P
D
) is given by P
D
e
(C
PD
a
C
L
) V
CC2
f
a
P
Q
where C
L
e
load capacitance f
e
frequency of operation for further details
see Application Note AN-90 ‘‘54C 74C Family Characteristics’’
